Forming method of silicon through hole interconnection structure

Abstract

The present invention provides a forming method of silicon through hole interconnection structure, comprising the steps of: supplying a substrate; forming a hard mask layer on a surface of the substrate; forming a photoresist pattern on a surface of the hard mask layer; regarding the photoresist pattern as a mask, etching the hard mask layer until the substrate is exposed; regarding the etched hard mask layer as the mask, etching the substrate with a first thickness by a piece of first etching equipment; regarding the etched hard mask layer as the mark, etching the substrate with a second thickness by a piece of second etching equipment, so as to form a through hole; wherein the uniformities of the first and second etching equipment at an edge area of the substrate and a centre area of the substrate are in a complementary relationship.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a through-silicon hole interconnection structure. Background technique [0002] In the past forty years, the research, development and production of microelectronic chips have been carried out along the prediction of Moore's Law; until 2008, companies such as Intel have begun to use 45nm to 50nm chips in the mass production of memory chips Line width processing technology. [0003] According to the prediction of Moore's Law, by 2012 at the latest, in order to further improve the integration of chips, it is necessary to use processing technology with a line width of 32 nanometers or even 22 nanometers. However, the 32nm or 22nm processing technology not only encounters the limitations of lithography equipment and process technology, but also has unresolved problems such as cell stability, signal delay, and CMOS circuit feasibility. [0004] For thi...

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Problems solved by technology

[0010] The process of etching the through hole by using the above-mentioned formation process of the through-silicon via interconnection structure usually adopts a plasma etching process. Due to the limitation of the uniformity of the existing etching process, refer to Image 6 , the etching speeds at the center position I of the wafer 100 and the edge position II of the wafer 100 are inconsistent, so that the through hole 101 formed by the same etching process is at the center position I of the wafer 100 and the edge position of the wafer 100 II depth is different, when making wafer thinning in step S104, refer to Figure 7 , through-holes with relatively shallow depths cannot expose conductive substances, resulting in failure of TSV interconnection structures

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