Method for realizing four-channel serial communication of SDRAM (Synchronous Dynamic Random Access Memory)

Abstract

The invention relates to a method for realizing four-channel serial communication of an SDRAM (Synchronous Dynamic Random Access Memory). The method comprises the steps of: transmitting command signals through one channel, and decoding command signals received from a serial channel D0 through a command control logic unit and recognizing the commands, wherein commands for serial four-channel SDRAM include a read operation command, a write operation command and an initialized configuration command; after the command control logic unit recognizes the initialized command, outputting a signal for configuring a PLL (Phase Locked Loop) and refreshing a counter, executing the configuring operations of configuring the PLL and refreshing the counter; after the command control logic unit recognizes the read and write commands, analyzing a received address signal to generate a column address, a row address and a BANK signal and sending the column address, the row address and the BANK signal to a column address latch decoder, a row address latch decoder and a BANK control logic; and then transmitting data signals, wherein the transmission of the data signals is controlled by a read-write register. The method changes the parallel communication mode of the SDRAM to the serial communication and realizes the four-channel serial communication function of the SDRAM.

Description

Technical field [0001] The present invention relates to the application field and serial communication field of SDRAM memory, in particular to a four-channel serial communication method for realizing SDRAM. Background technique [0002] The relevant technical background of SDRAM is as follows: [0003] 1. SDRAM pin classification [0004] (1) Address signal port: BANK signal port (BA0, BA1), row address and column address multiplexing port (A0~A11). [0005] (2) Data signal port: bidirectional pins (D0~D15), controlled by read and write commands and data mask port (DQM). [0006] (3) Control signal port: clock enable port (CKE), command port including chip selection (CS) and row and column address selection (CAS, RAS), read and write valid (WE). The command code is shown in the table: [0007] [0008] 2. SDRAM addressing mode [0009] The BA0 and BA1 ports receive the BANK selection signal, and select the BANK through the L_BANK control logic. The address lines A0~A11 are the column ad...

AI Technical Summary

Problems solved by technology

[0015] The purpose of the present invention is to solve the problem that the SDRAM memory cannot communicate with external equipment serially, and provide a four-channel serial communication method for realizing SDRAM

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