Method and processor for encryption and decryption

An encryption and decryption, processor technology, applied in the field of methods and processors, can solve problems such as occupying more FPGA area

Active Publication Date: 2017-06-23
北京京航计算通讯研究所
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, to introduce support for subroutine calls in the processor, this solution needs to occupy a certain amount of FPGA area

Method used

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  • Method and processor for encryption and decryption
  • Method and processor for encryption and decryption

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Embodiment Construction

[0024] Specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. In the following description, for purposes of explanation and not limitation, specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details.

[0025] It should be noted here that, in order to avoid obscuring the present invention due to unnecessary details, only the device structure and / or processing steps closely related to the solution according to the present invention are shown in the drawings, and the steps related to the present invention are omitted. Invent other details that don't really matter.

[0026] An embodiment of the present invention provides a processor for encryption and decryption, such as figure 1 As shown, it includes: a secret key ...

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Abstract

The invention discloses a method and processor for encryption and decryption, relates to the encryption and decryption technology and effectively reduces the logic unit number occupied by ARS during FPGA realization. According to the method, input data is stored in an input data register, and a data storage address addr=addr1+addr8 is updated; if a reading of a cycle counter is smaller than a cycle counting number in an instruction, an index register and the cycle counter are respectively plus one, transfer to an instruction address designed by addr8 is then carried out, zero setting of the cycle counter is carried out, and cycle operation in a 0-15 scope is realized; original data of the register is stored to another register when register writing operation is simultaneously carried out, reading operation from a storage device to the register and writing operation from the register to another register is combined to one same instruction, a 16-times cycle program block is realized through six instructions, and the method is for encryption and decryption.

Description

technical field [0001] The present invention relates to the technical field of encryption and decryption, in particular to a method and processor for encryption and decryption. Background technique [0002] AES is an encryption and decryption algorithm with high popularity and good reliability. The algorithm was proposed in 1998, and was soon designated as an advanced encryption standard by the National Institute of Standards and Technology (NIST), and became widely popular internationally after 2006. [0003] The secret key of the AES algorithm is divided into three types: 128-bit, 192-bit and 256-bit. The 128-bit version is generally used for mass products, and the 256-bit version is available for top secrets. [0004] In terms of implementation technology, the AES algorithm is divided into software implementation, FPGA implementation and ASIC implementation. Software implementation is cheap and flexible, and ASIC implementation is expensive and high performance. FPGA ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L9/06
Inventor 陈钢闫昆李娜魏伟波魏鑫张志刚王杰王颖舒毅吕宗辉于润泽
Owner 北京京航计算通讯研究所
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