Method and device for increasing read-write rate of double data rate synchronous dynamic random access memory

Abstract

The invention provides a method and a device for increasing the read-write rate of a double data rate synchronous dynamic random access memory (DDRSDRAM). The method comprises the following steps of: receiving a read address corresponding to a read request of a packet; caching the read address in a corresponding first first-in first-out queue (FIFO) according to a bank number; reading the read address out from a first FIFO in the first FIFO for the first time; if the next read address in the first FIFO and the read address read out for the first time belong to same-line addresses, continuously reading the first FIFO; and if the next read address in the first FIFO and the read address read out for the first time belong to different-line addresses, reading the next first FIFO in a polling mode. By the method and the device for increasing the read-write rate of the DDRSDRAM, realization difficulties are reduced, the realizability and the adjustment force of a field programmable gate array (FPGA) project are improved, and the read-write efficiency of the DDRSDRAM is greatly improved by limited resources.

Description

Technical field [0001] The invention relates to the field of data communication, as it relates to a method and a device for increasing the reading and writing rate of a double data rate synchronous random access memory. Background technique [0002] Double Data Rate Synchronous Random Access Memory (DDR SDRAM) is a new generation memory technology standard released by the Joint Electronic Equipment Engineering Committee (JEDEC) in 2004. [0003] Because of its low price, high bandwidth data throughput and low power consumption advantages, double data rate synchronous random access memory is widely used in data communication fields with high storage requirements. However, in the field of data communication chips, the key performance index of the chip processing packets per second (pps) determines that the double data rate synchronous random access memory used for data packet buffering must achieve the lowest read and write efficiency to meet the processing capacity of the chip. At ...

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Problems solved by technology

The activation time of DDR SDRAM row closing is relatively long. At the same time, if it is an interval of read and write operations, there must be a certain time interval between read->write switching and writing->read switching. It is precisely because of these inherent time intervals Due to the limitation of DDR SDRAM, the reading and writing efficiency of DDR SDRAM is often the performance bottleneck of data communication projects

[0006] In the prior art, there is a method for sorting the read and write addresses of the double data rate synchronous random access memory respectively. This method sorts the read and write commands sent by the user inside the DDR controller, in order to send double data Before the rate synchronous random memory, the read and write commands are arranged into an ideal read and write sequence, and the addresses of different rows of the same bank are staggered as much as possible. The biggest hidden danger of this technology is that excessive reordering may cause the data packet to not be written. DDR SDRAM was initiated before the read request

At present, there are technologies that can reorder about 8 read and write commands to hide the line closing time of the two commands before and after DDR SDRAM. Although this technology can perform commands between banks and different lines of the same bank between 8 commands order adjustment, but the order adjustment function of commands and the reordering of DDR read data are more complicated, it is difficult to make a big breakthrough in hardware frequency, and consumes a lot of resources, and the adjustment ability is limited. Field programmable gate array (FPGA) project does not have very good feasibility

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