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Interfacial layers for electromigration resistance improvement in damascene interconnects

A dielectric layer, dielectric technology, applied in the direction of circuits, electrical components, electrical solid devices, etc.

Active Publication Date: 2011-07-20
NOVELLUS SYSTEMS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The fabrication of these interconnects presents several challenges that are becoming more apparent as the dimensions of IC device features continue to shrink

Method used

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  • Interfacial layers for electromigration resistance improvement in damascene interconnects
  • Interfacial layers for electromigration resistance improvement in damascene interconnects
  • Interfacial layers for electromigration resistance improvement in damascene interconnects

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Experimental program
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Embodiment Construction

[0044] Introduction and Review

[0045] As device dimensions continue to decrease and interconnects experience increasing current densities, electromigration is becoming a significant reliability issue in IC manufacturing. Electromigration is manifested by the migration of metal atoms with an electric current and the formation of voids within the interconnect. The formation of voids can subsequently lead to device failure. The migration of metal atoms is particularly pronounced at the metal / diffusion barrier interface and along grain boundaries. Currently, at the 90nm and 45nm technology nodes, methods for improving electromigration performance are needed.

[0046] Although electromigration performance can be improved by introducing dopant elements into interconnects, such dopants typically have a higher resistivity than the interconnect metal (e.g., Cu) and can significantly increase interconnect resistance. Thus, uncontrolled doping of the interconnect metal can result i...

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Abstract

Protective caps residing at an interface between metal lines and dielectric diffusion barrier (or etch stop) layers are used to improve electromigration performance of interconnects. Protective caps are formed by depositing a first layer of aluminum-containing material over an exposed copper line by treating an oxide-free copper surface with an organoaluminum compound in an absence of plasma at a substrate temperature of at least about 350 DEG C. The formed aluminum-containing layer is passivated either partially or completely in a chemical conversion which forms Al-N, Al-O or both Al-O and Al-N bonds in the layer. Passivation is performed in some embodiments by contacting the substrate having an exposed first layer with an oxygen-containing reactant and / or nitrogen-containing reactant in the absence of plasma. Protective caps can be formed on substrates comprising exposed ULK dielectric. The aluminum-containing layer residing on the dielectric portion will typically spontaneously form non-conductive layer comprising Al-O bonds.

Description

technical field [0001] The present invention relates to methods of forming layers of material on partially fabricated integrated circuits. In particular, the present invention relates to methods of forming protective caps within copper lines to improve the electromigration characteristics of damascene interconnects. Background technique [0002] Damascene processing is a method of forming metal lines on integrated circuits. It involves forming embedded metal lines in trenches and vias formed in a dielectric layer (interlayer dielectric). Damascene processing is generally the preferred method because it requires fewer processing steps than other methods and provides higher yields. It is also particularly well suited for metals such as copper that cannot be easily patterned by plasma etching. [0003] In a typical damascene process flow, metal is deposited into a patterned dielectric to fill the vias and trenches formed in the dielectric layer. The resulting metallization ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768H01L21/00H01L23/532
CPCH01L2924/0002H01L2924/00H01L21/02046H01L21/02247H01L21/0228H01L21/02315H01L21/28247H01L21/324H01L21/76807H01L21/76834H01L21/0262
Inventor 阿南达·班纳吉乔治·安德鲁·安东内利詹尼佛·奥洛克林曼蒂阿姆·斯里拉姆巴尔特·范施拉文迪杰克塞莎赛义·瓦拉达拉詹
Owner NOVELLUS SYSTEMS