Test structure and method for measuring HCI (hot carrier injection) reliability of MOS (metal oxide semiconductor) device
A MOS device and test structure technology, which is applied in the direction of single semiconductor device testing, semiconductor devices, electric solid state devices, etc., can solve the problems of MOS device lateral electric field and channel effective electric field increase, so as to shorten the time of reliability measurement, reduce the Small layout area, the effect of improving efficiency
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[0025] The specific implementation of the present invention will be further described in detail below in conjunction with the drawings and embodiments. The following examples are used to illustrate the present invention, but not to limit the scope of the present invention.
[0026] The present invention provides a test structure capable of simultaneously measuring the HCI reliability of n-type and p-type MOS devices (MOSFET devices in this embodiment). Such as figure 2 As shown, this structure combines the HCI test structure of n-type and p-type MOSFET devices. The source Sn of the n-type MOSFET device, the substrate Sub-n and the drain Dp of the p-type MOSFET device are internally connected to Together they constitute the source of the structure of the present invention. At the same time, the source Sp of the p-type MOSFET device, the substrate Sub-p, and the drain Dn of the n-type device are also connected together to form the drain of the structure of the present invention. ...
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