Unlock instant, AI-driven research and patent intelligence for your innovation.

Test structure and method for measuring HCI (hot carrier injection) reliability of MOS (metal oxide semiconductor) device

A MOS device and test structure technology, which is applied in the direction of single semiconductor device testing, semiconductor devices, electric solid state devices, etc., can solve the problems of MOS device lateral electric field and channel effective electric field increase, so as to shorten the time of reliability measurement, reduce the Small layout area, the effect of improving efficiency

Active Publication Date: 2012-12-05
PEKING UNIV
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to the shrinking of the device size, the lateral electric field and the effective electric field of the channel increase in the MOS device

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Test structure and method for measuring HCI (hot carrier injection) reliability of MOS (metal oxide semiconductor) device
  • Test structure and method for measuring HCI (hot carrier injection) reliability of MOS (metal oxide semiconductor) device
  • Test structure and method for measuring HCI (hot carrier injection) reliability of MOS (metal oxide semiconductor) device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0025] The specific implementation of the present invention will be further described in detail below in conjunction with the drawings and embodiments. The following examples are used to illustrate the present invention, but not to limit the scope of the present invention.

[0026] The present invention provides a test structure capable of simultaneously measuring the HCI reliability of n-type and p-type MOS devices (MOSFET devices in this embodiment). Such as figure 2 As shown, this structure combines the HCI test structure of n-type and p-type MOSFET devices. The source Sn of the n-type MOSFET device, the substrate Sub-n and the drain Dp of the p-type MOSFET device are internally connected to Together they constitute the source of the structure of the present invention. At the same time, the source Sp of the p-type MOSFET device, the substrate Sub-p, and the drain Dn of the n-type device are also connected together to form the drain of the structure of the present invention. ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a test structure for measuring HCI (hot carrier injection) reliability of an MOS (metal oxide semiconductor) device. The test structure comprises an n-type MOS device and a p-type MOS device, wherein the source and the substrate of the n-type MOS device and the drain of the p-type MOS device are connected together to form the source of the structure; the source and the substrate of the p-type MOS device and the drain of the n-type device are connected together to form the drain of the structure; and the grids of the n-type MOS device and the p-type MOS device form the n-type grid and p-type grid of the structure respectively. The invention provides a test structure and method capable of measuring the HCI reliability of the n-type MOS device and p-type MOS device atthe same time, so that the HCI reliability test for the n-type MOSFET (metal oxide semiconductor field effect transistor) device and the p-type MOSFET device can be implemented on the same test structure.

Description

Technical field [0001] The invention relates to the field of MOS device reliability research, in particular to a test structure and method for measuring the reliability of MOS device HCI (Hot Carrier Injection). Background technique [0002] With the rapid development of semiconductor technology and the substantial increase in the integration of microelectronic chips, the design and processing level of integrated circuits has entered the era of nano MOS. The resulting performance degradation of nano MOS devices and factors affecting device reliability continue to appear. . As the device size shrinks, the lateral electric field and channel effective electric field increase in MOS devices. At the same time, the HCI degradation caused by pMOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) has become equivalent to the HCI degradation of nMOSFET. In order to obtain the HCI degradation law of n and p-type MOSFET devices, The conventional test method is to use the HCI test str...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/544H01L27/02G01R31/26
CPCH01L2924/0002
Inventor 何燕冬张钢刚刘晓彦张兴
Owner PEKING UNIV
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More