A kind of asymmetric gate MOS device and its preparation method
A MOS device, asymmetric technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of asymmetric gate field effect transistor process difficulty, difficult to control, etc., to achieve overall performance parameter optimization, method Simple and convenient effect
Inactive Publication Date: 2017-04-12
FUDAN UNIV
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[0008] However, the above-mentioned method of preparing an asymmetric gate field effect transistor by forming a gate oxide layer with an inconsistent thickness on the source terminal and the drain terminal of the transistor has certain difficulties in the process, and it is difficult to achieve better control.
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[0055] The asymmetric gate MOS device and its preparation method proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in very simplified form and use imprecise ratios, which are only used for the purpose of conveniently and clearly assisting in describing the embodiments of the present invention.
[0056] The core idea of the present invention is to provide an asymmetric gate MOS device, the gate of which is a metal gate, and the work function of the metal gate is different at the source end and the drain end of the MOS device, so that the overall performance of the MOS device The parameters are more optimized; at the same time, a method for preparing an asymmetric gate MOS device is also provided, the method performs ion implantation...
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Abstract
The invention discloses an asymmetric gate MOS device, the gate of which is a metal gate, and the work function of the metal gate is different at the source end and the drain end of the MOS device, so that the overall performance parameters of the MOS device are more optimized; At the same time, it also discloses a preparation method of an asymmetric gate MOS device. The method performs ion implantation doping on the gate of the MOS device, so that the work function of the gate is at the source end and the drain end of the MOS device. Different, so that the overall performance parameters of the MOS device are more optimized, the method is simple and convenient.
Description
technical field [0001] The invention relates to the technical field of semiconductor technology, in particular to an asymmetric gate MOS device and a preparation method thereof. Background technique [0002] After decades of rapid development since the invention of the first transistor, the horizontal and vertical dimensions of transistors have shrunk rapidly. According to the prediction of International Technology Roadmap for Semiconductors (ITRS) in 2004, the feature size of transistors will reach 7nm by 2018. The continuous shrinking of the size has continuously improved the performance (speed) of the transistor, and also enabled us to integrate more devices on the chip of the same area. The function of the integrated circuit has become stronger and stronger, and the cost per unit function has also been reduced. [0003] However, the continuous reduction of device feature size also brings a series of challenges. When the feature size of the device enters deep submicron,...
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IPC IPC(8): H01L29/78H01L29/49H01L21/336
CPCH01L21/2815H01L21/26586H01L21/28097H01L21/28105H01L29/4975H01L29/66575H01L29/66659H01L21/28008H01L21/28518H01L29/04H01L29/6659H01L29/7835
Inventor 吴东平胡成朱伦朱志炜张世理张卫
Owner FUDAN UNIV