High-reliability power supply clamping ESD (Electronic Static Discharge) protection circuit

Abstract

The invention relates to the technical field of integrated circuit chip ESD (Electronic Static Discharge) protection, in particular to a high-reliability power supply clamping ESD protection circuit. The ESD protection circuit comprises a capacitor-resistor module (1), a clamping transistor open module (2), a clamping transistor (4) which are connected in sequence; the ESD protection circuit also comprises a clamping transistor close module (3) which is respectively connected with the capacitor-resistor module (1) and the clamping transistor (4). According to the invention, through separating a circuit structure used for controlling the open and close of the clamping transistor, the clamping transistor can obtain enough open time under the condition that of the capacitor-resistor module in the ESD protection circuit has very small time constant.

Description

technical field [0001] The invention relates to the technical field of electrostatic discharge (ESD) protection of integrated circuit chips, in particular to a high-reliability power clamp ESD protection circuit. Background technique [0002] In the process of integrated circuit chip manufacturing, packaging, testing, transportation and use, there are many different electrostatic discharge modes. When these electrostatic charges accumulate on the gate of the MOS transistor, due to the small gate capacitance of the MOS transistor , These electrostatic charges will form a large equivalent gate voltage, resulting in the failure of the device or circuit, which is the ESD problem. Along with the scaling down of integrated circuit feature size, the gate oxide layer is made thinner and thinner, which makes ESD protection more difficult and important in nanometer-scale device and circuit design. [0003] An integrated circuit chip is mainly connected with the outside world through ...

AI Technical Summary

Problems solved by technology

[0005] figure 1 Although the circuit shown is logically sound, as the size of the device shrinks, the reliability of its ESD protection performance faces a huge challenge

The continuous shrinking of the feature size of integrated circuits will inevitably require the R-C part of the ESD protection module to be as small as possible. Since the gate voltage of Mbig is pulled down after the R-C time constant has passed, the reduction of the R-C time constant will lead to a decrease in the turn-on time of Mbig. Shorten, which may lead to incomplete release of ESD charges and damage to internal circuits

On the other hand, for the fast-rising normal power-on voltage, it is hoped that the clamping transistor will not be turned on, that is, the ESD protection circuit will not be triggered by mistake, so the ESD protection circuit with strong anti-false trigger capability also requires the R-C time constant to be made very small , which would also contradict the sufficiently long turn-on time of the clamp transistor

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