Method and device for checking field programmable gate array (FPGA)

Abstract

The embodiment of the invention discloses a method and a device for checking a field programmable gate array (FPGA) and relates to the field of integrated circuit design. Various intellectual property (IP) core checking requirements can be met and the universality is high. The method comprises the following steps of: compiling a preset exciting demand into a machine code, wherein the preset exciting demand is described by using a preset instruction set and the machine code can be identified by a processor; executing the machine code by the processor and generating exciting data; inputting the exciting data into a module to be detected; and checking whether the module to be detected is correct according to an output result of the module to be detected. The invention is mainly applied to checking the FPGA.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a method and device for FPGA verification. Background technique [0002] With the progress of integrated circuit process technology and the improvement of integrated circuit design level, more and more memory controller IP cores (intellectual property cores, Intellectual Property cores) are integrated into a system chip (SoC). If you want to perform FPGA prototype verification on the system chip, or integrate the IP core into the FPGA-based system chip, in order to ensure that the memory controller IP core can work normally on the FPGA platform, you need to verify the memory controller IP core. [0003] Since the SoC with DDR / DDR2 / DDR3 SDRAM controller, NAND / NOR Flash ROM controller, and 32-bit CPU (central processing unit) is more complicated, when the SoC is transplanted to the FPGA platform as a whole and the FPGA prototype is verified, It is difficult to locate the d...

AI Technical Summary

Problems solved by technology

[0005] However, in the prior art, when verifying each IP core, since the incentive requirements of each IP core are realized by a set of dedicated hardware, when it is necessary to verify multiple IP cores, it is necessary to build multiple Corresponding hardware structure, the types of IP cores that can be processed by the same test platform are limited, and the versatility is poor

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