Site yield statistical method for multi-site parallel test

Abstract

The invention discloses a method for determining the state of testing hardware by using statistical test data in the process of testing a wafer of an integrated circuit. The test data generated in the process of testing the wafer reflects the physical parameter of each chip, the function of an internal module, a manufacturing process of each chip, and the state of the testing hardware in the testing process. By a site yield statistical method for a multi-site parallel test, whether the state of the testing hardware in the testing process is defective or not is checked. By the method, the yield of each site is obtained through the statistical induction of massive test data, and specific bin value distribution is obtained, so that the failure cause of the testing hardware can be quickly found, solution measures are taken, and test quality is ensured.

Description

technical field [0001] The invention relates to a method for detecting equipment status by using statistical test data in the process of testing an integrated circuit wafer, and belongs to the technical field of integrated circuit testing. Background technique [0002] At present, in the process of developing new products, especially in mass production, chip design companies and testing factories mainly judge whether the physical parameters and module functions inside the chip are good or not based on the massive data generated during the testing process, and further confirm the wafer manufacturing process. Whether the process or packaging process meets the design requirements. These test information are all for the detection of the chip itself. However, when the chip test results fail due to non-chip internal failures, it is difficult to determine which factors cause the chip failure. The usual methods are shutdown, Interrupt the test process, software engineers and hardwa...

AI Technical Summary

Problems solved by technology

These test information are all for the detection of the chip itself. However, when the chip test results fail due to non-chip internal failures, it is difficult to determine which factors cause the chip failure. The usual methods are shutdown, Interrupt the test process, software engineers and hardware engineers analyze the reasons together, use measuring instruments to check whether the channel of the tester is in good contact with the chip under test, or remove the probe card to check whether the probes are contaminated, etc.; Links and interfaces are checked, and faults are eliminated one by one, which prolongs the downtime, affects the test output, and reduces the test efficiency

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