Method for manufacturing crystal grain assembly

Abstract

The invention relates to a method for manufacturing a crystal grain assembly. The method comprises the following steps: (a) providing a tested upper wafer and at least one lower wafer; (b) cutting the at least one lower wafer, thereby forming a plurality of lower crystal grains containing a plurality of known qualified crystal grains; (c) according to a wafer map of the upper wafer, selecting andrearranging the known qualified crystal grains on a carrier; (d) connecting the upper wafer to the carrier; (e) removing the carrier; and (f) performing a cutting process. The method can be used for ensuring that the crystal grains of the crystal grain assembly are all known qualified crystal grains, thereby avoiding the yield loss caused by different yields of the upper wafer and the lower wafer.

Description

technical field [0001] The present invention relates to a die assembly and a manufacturing method thereof, in particular, to a die assembly manufactured by wafer-to-wafer stacking and a manufacturing method thereof. Background technique [0002] At present, the three-dimensional IC packaging method mainly adopts two stacking technologies: one is wafer-to-wafer (WtW) stacking; the other is chip-to-chip (CtC) stacking or chip-to-wafer (Chip to Wafer, CtW) stack. Compared with chip-to-chip (CtC) stacking or chip-to-wafer (CtW) stacking, wafer-to-wafer (WtW) stacking is a method that can achieve A packaging method with high output and simpler process steps. [0003] However, the biggest disadvantage of the wafer-to-wafer (WtW) stacking process is that the output will be affected by the yield rate of the upper and lower wafers. For example, the yield rates of the two wafers to be stacked are respectively 50% and 100%, even if one of the wafers has a higher yield, after the two...

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Problems solved by technology

[0003] However, the biggest disadvantage of the wafer-to-wafer (WtW) stacking process is that the output will be affected by the yield rate of the upper and lower wafers. For example, the yield rates of the two wafers to be stacked are respectively 50% and 100%, even if one of the wafers has a higher yield, after the two wafers are directly stacked on each other, the yield of qualified products is only 50%, and the yield loss (Yield Loss) is as high as 50%

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