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Integrated Circuit Test Methods

A technology of integrated circuits and test systems, which is applied in the field of testing storage components and can solve problems such as time-consuming

Inactive Publication Date: 2011-12-14
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] This test is a time consuming process as the integrated circuits are tested individually

Method used

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Embodiment Construction

[0033] In order to make the above-mentioned content and other aspects of this disclosure more obvious and understandable, the preferred embodiments are specifically cited below, together with the accompanying drawings, and are described in detail as follows:

[0034] figure 1 Shown is a partial block diagram of an integrated circuit testing system 100 . Integrated circuit test system 100 includes a commercial test system, such as Kalos 1 . Integrated circuit test system 100 may allow parallel testing of a limited number of test elements. The integrated circuit testing system 100 includes a tester 102 , a multiplexer 104 , and a probe card 106 . In some embodiments, one or both of the tester 102 and the multiplexer 104 may be physically integrated into the probe card 106 . The probe card 106 includes a plurality of test points S0-S15, and each test point S0-S15 can independently test a respective integrated circuit (test element). In particular, if figure 1 In the illustra...

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PUM

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Abstract

An integrated circuit testing method includes providing an integrated circuit testing system with a voltage supply and a plurality of control channels. A first switch element is connected between the voltage supply and a first integrated circuit, and a second switch element is connected between the voltage supply and the second integrated circuit. The switching element may comprise, for example, an electromagnetic relay. The relay can be controlled by the corresponding test system control channel to selectively provide power to each integrated circuit.

Description

technical field [0001] The present invention relates to the testing of an integrated circuit, and in particular to the testing of a memory element. Background technique [0002] The fabrication of integrated circuits involves processing a chip through a series of fabrication steps to create multiple integrated circuits on the chip. Once the chip manufacturing process is completed, the chip is diced into individual integrated circuits, and then these individual integrated circuits go through different wire bonding and packaging steps. Before these integrated circuits are used, however, it is desirable to be able to test the operation of these integrated circuits. In some cases, integrated circuits may be tested prior to die dicing. Alternatively, the integrated circuit can be tested after the wire bonding and packaging steps. Generally, these tests are done to verify the different electrical properties of integrated circuits. The information obtained from the tests can be...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28G01R31/30
Inventor 吴明锡
Owner MACRONIX INT CO LTD
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