Simple single-bus interface conversion circuit and data acquisition system adopting same

Abstract

The invention discloses a simple single-bus interface conversion circuit. At least two three-state buffers drive sending of data, so transmission capacity is transmitted; and a single-bus end is grounded by a pull-down resistor, so the anti-interference capacity of sending of the data is improved. Meanwhile, after the three-state buffers amplify input data which is input to a data input end of a logical AND gate, the input data is input to a serial point of two input resistors, which are connected in series, of the logical AND gate by output resistors which are connected in parallel and capacitors, so the input data is amplified in the forward direction, the signal strength of the input data of the data input end of the logical AND gate is improved, and the receiving stability of the datais improved. Moreover, a microprocessor is adopted to control the sending and receiving of the data; during the sending of the data, the logical AND gate is closed, and the input data is not received, so the sending of the data cannot influence a receiving end of the microprocessor; and burrs are avoided from being formed at the receiving end of the microprocessor during the sending of the data in the prior art, so communication reliability is reduced.

Description

technical field [0001] The invention belongs to the technical field of interface circuits, and more specifically relates to a simple single-bus interface conversion circuit and a data acquisition system for its application. Background technique [0002] Most microprocessors have a universal asynchronous transceiver inside, and there are usually two communication lines on the hardware, one is a receiving line and the other is a sending line. However, in some applications, especially for applications where the communication distance and communication rate are not high, but the space requirements are extremely strict, and it is impossible to design a transceiver interface circuit with a tri-state gate, it can only be designed as a communication line. The single-bus interface is not only easy to install, but also reduces wiring costs for applications that do not require high communication distance and communication speed. [0003] The existing conversion circuit from the univer...

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Problems solved by technology

[0005] However, in the above-mentioned single-bus interface conversion circuit, the output of the NAND gate is used to drive and send data to the single bus, and the driving ability is not strong, so that the transmission distance of the single bus is small and the transmission capacity is low; the NAND gate is used to directly receive data from the single bus. The data on the bus is susceptible to interference, and the stability of data reception is poor. In addition, although the sending signal is theoretically, no low-level interrupt signal will be generated at the receiving end RXD of the microprocessor, but due to the delay of the three-level NAND gate When the output signal of the microprocessor changes from low to high, the two ends of the output NAND gate (U2A) will be high level, so there will be a glitch in which the output of the NAND gate (U2A) is low level. The receiving end RXD of the microprocessor will generate a low-level interrupt signal, which reduces the reliability of communication

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