A high-precision pulse width comparison device based on time-to-digital conversion

Abstract

The invention discloses an automatic frequency comparison circuit using a high-precision pulse width comparison device based on time-to-digital conversion. On the basis of the automatic frequency calibration device of the original phase-locked loop of the present invention, a DLL module is added to generate a plurality of delayed phase clocks with the same frequency and phase difference as the reference clock, and simultaneously count the reference clock and its delayed clock and accumulate all counter results, At the same time, the feedback clock is counted, and the capacitor array is adjusted by comparing the accumulated value of the reference clock and its delayed clock counter with the value of the feedback counter. Only need to add a DLL delay phase-locked loop circuit on the circuit, the frequency resolution can be greatly improved, the frequency difference between the reference clock and the feedback clock can be distinguished with higher precision, the automatic calibration time is greatly reduced, and the phase-locked loop lock is shortened. Time, so it can meet the needs of modern communication systems for fast switching of phase-locked loop frequencies.

Description

technical field [0001] The invention is applicable to communication systems, and relates to a high-precision pulse width comparison device based on time-to-digital conversion technology used in an AFC (Auto frequency correction) automatic frequency calibration circuit in a radio frequency integrated circuit chip phase-locked loop. Background technique [0002] At present, in modern communication systems, radio frequency chips often need to cover a wide frequency range, which is beyond the range covered by the VCO (Voltagecontrolloscillator voltage-controlled oscillator) by adjusting the voltage. The PLL phase-locked loop (PhaseLockLoop phase-locked loop) is The RF chip provides a local oscillator, so it needs to be able to lock normally in a large frequency range. Such as figure 1 As shown, the existing phase-locked loop adds an adjustable capacitor array to the VCO to increase the VCO frequency adjustable range. In a larger frequency range, the VCO can lock and maintain a ...

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Problems solved by technology

However, since the frequency difference between the reference clock frequency and the feedback clock frequency is not large, it takes a long time to count to divide the frequency difference, resulting in too long time for the output clock of the phase-locked loop to stabilize, which cannot meet the fast switching of clock frequency in the communication system. Require

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