Multi-thread processor, compiler device and operating system device

A multi-threaded processor and compiler technology, applied in multi-programming devices, machine execution devices, code compilation, etc., can solve the problems of thread execution efficiency reduction, waste, and inability to execute at the same time, and achieve high execution efficiency and high efficiency The effect of using

Active Publication Date: 2012-01-25
SOCIONEXT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the two threads cannot be executed at the same time and only the commands of a certain thread are executed.
Therefore, one or two arithmetic unit resources are not used to cause waste, and there is a problem that the execution efficiency of the thread is reduced.

Method used

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  • Multi-thread processor, compiler device and operating system device
  • Multi-thread processor, compiler device and operating system device
  • Multi-thread processor, compiler device and operating system device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0056] In this embodiment, a multi-threaded processor that improves command execution efficiency through command execution control, limitation of the number of commands, designation of the limited number of commands by registers, designation of the limited number of commands by commands, and the number of execution cycles will be described. Designation of intervals, designation of execution cycle intervals by registers, command-based designation of execution cycle intervals, and suppression of issue intervals of commands with resource constraints.

[0057] figure 1 It is a block diagram showing the structure of the multi-thread processor of this embodiment. In addition, in this embodiment, it is assumed that it is a multi-threaded processor capable of executing three threads in parallel.

[0058] The multithreaded processor 1 includes: an instruction memory 101, a first instruction decoder 102, a second instruction decoder 103, a third instruction decoder 104, a first instru...

Embodiment approach 2

[0109] Next, a compiler and an operating system according to Embodiment 2 of the present invention will be described with reference to the drawings.

[0110] Figure 5 It is a block diagram showing the configuration of the compiler 3 according to Embodiment 2 of the present invention.

[0111]Compiler 3 accepts source program 301 described by a programmer in C language as input, converts it into an internal intermediate representation (intermediate code), performs optimization and resource allocation, and generates executable code 302 suitable for the target processor. The processor targeted by the compiler 3 is the multithreaded processor 1 described in the first embodiment.

[0112] Next, the detailed structure and operation of each component of the compiler 3 of the present invention will be described. In addition, the compiler 3 is a program, and its function is realized by executing the program for realizing each component of the compiler 3 on a computer having a proces...

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PUM

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Abstract

A multi-thread processor (1) which executes instructions in multiple threads in parallel is provided with a computing unit group (119) comprising multiple computing units each for executing an instruction, a first instruction grouping unit (108) to a third instruction grouping unit (110) each for, in each thread, grouping instructions included in the thread into a group comprising instructions concurrently executable by the multiple computing units, a thread selection unit (114) for selecting, from among the multiple threads, a thread including instructions to be issued to the multiple computing units at every execution cycle of the multi-thread processor (1) by controlling the frequency of execution of the instructions in the multiple threads, and an instruction issuance control unit (115); for issuing the instructions of the grouped group among instructions included in the thread selected by the thread selection unit (114) to the multiple computing units at every execution cycle of the multi-thread processor (1).

Description

technical field [0001] The present invention relates to a multi-thread processor and the like that execute a plurality of threads in parallel, and more particularly to a multi-thread processor and the like that improve the execution efficiency of each thread by controlling the execution timing of commands contained in each thread. Background technique [0002] In recent years, in the field of AV (Audio / Visual) processing, new codecs (codecs) and new specifications have been continuously announced, and the demand for AV processing based on software has been increasing. Therefore, the performance of the processor required in the AV system and the like has also increased dramatically. Also, in response to multitasking of executed software, many multithreaded processors employing a multithreading technique for executing a plurality of threads simultaneously have been developed. [0003] Among conventional multithreaded processors, there is known a technique of fine-grained mult...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38G06F9/46
CPCG06F9/3853G06F9/3851G06F8/45
Inventor 古贺义宏瓶子岳人
Owner SOCIONEXT INC
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