The invention provides a method and a device for
fault tolerance of a grading
instruction memory structure capable of actively writing back. The device comprises a grading
instruction memory, an instruction fault correcting and checking module, an instruction character register, and an instruction address register. The method comprises: 1, starting and operating a processor; 2, taking out instruction character data from the grading
instruction memory; 3, sending the instruction character data to the instruction fault correcting and checking module; 4, determining a fault correcting and checking result to have no fault or have a correctable fault; if yes, continuing to perform a step 5; if no,
jumping to step 10; 5, writing an instruction character to the instruction character register; 6,updating the instruction address register; 7, determining whether a correctable fault occurs; if yes, continuing to perform a step 8; if no,
jumping to a step 9; 8, writing the instruction character data back to the grading instruction memory; 9, ending
processing;
jumping to the step 2,
processing the address of the next instruction; 10, when the instruction character data has uncorrectable fault, suspending the processor. The method and the device realize
fault tolerance of instructions and the instruction memory, and have relatively low hardware cost.