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Method for manufacturing semiconductor device structure comprising stress layer

A device structure and stress layer technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of uniform stress application and deterioration of the overall electrical performance of semiconductor devices, so as to improve the uniformity and improve the overall electrical performance. performance, the effect of improving the profile

Active Publication Date: 2013-10-30
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In addition, if figure 2 As shown in 202, the cross-sectional profile of the sidewall is bow-shaped, so that the stress cannot be uniformly applied to the channel in the vertical direction, both of which will lead to the deterioration of the overall electrical performance of the final semiconductor device

Method used

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  • Method for manufacturing semiconductor device structure comprising stress layer
  • Method for manufacturing semiconductor device structure comprising stress layer
  • Method for manufacturing semiconductor device structure comprising stress layer

Examples

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no. 1 example

[0038] Below, will refer to Figures 3A to 3F as well as Figure 4 A method for manufacturing a semiconductor device structure including a stress layer according to a first embodiment of the present invention will be described in detail. Figures 3A to 3F is a schematic cross-sectional view showing steps of a method for manufacturing a semiconductor device structure including a stress layer according to a first embodiment of the present invention.

[0039] First, if Figure 3A As shown in , a front-end device structure is provided. The front-end device structure includes a silicon-based substrate 301 and a gate structure 310 formed on the silicon-based substrate, wherein the gate structure 310 includes a silicon-based substrate formed on the silicon-based substrate. A gate oxide layer 302 on the bottom 301 and a polysilicon gate 303 formed on the gate oxide layer 302 . The silicon-based substrate 301 can be made of undoped single crystal silicon or single crystal silicon do...

no. 2 example

[0057] Next, we will refer to Figure 6A A method for manufacturing a semiconductor device structure including a stress layer according to a second embodiment of the present invention will be described. Figure 6A Schematically shows He and O according to this embodiment 2 An example of the variation curve of the flow rate ratio between.

[0058] According to the second embodiment of the present invention, in the process of etching a silicon-based substrate to form grooves, He and O in the etching source gas 2 The flow rate ratio between them has a non-linear decreasing trend with time, except that, the second embodiment according to the present invention is the same as the first embodiment according to the present invention in other respects.

[0059] Such as Figure 6A As shown in , He and O in the etching source gas 2 The flow rate ratio between them has a non-linear decreasing trend with time, and the change curve is a convex curve. Among them, the He and O 2 The flo...

no. 3 example

[0061] Next, we will refer to Figure 6B A method for manufacturing a semiconductor device structure including a stress layer according to a third embodiment of the present invention will be described. Figure 6B Schematically shows He and O according to this embodiment 2 Another example of the variation curve of the flow rate ratio between.

[0062] Similar to the second embodiment of the present invention, according to the third embodiment of the present invention, in the process of etching a silicon-based substrate to form grooves, He and O in the etching source gas 2 The flow rate ratio between them also has a nonlinear decreasing trend with time. The difference is that in this example, He and O 2 The change curve of the flow rate ratio between is a concave curve rather than a convex curve. Except for this, the third embodiment according to the present invention is the same as the first and second embodiments according to the present invention in other respects.

[00...

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Abstract

The invention provides a method for manufacturing a semiconductor device structure comprising a stress layer. The method comprises the following steps: providing a front-end device structure, wherein the front-end device structure comprises a silicon-based substrate and a grid structure formed on the silicon-based substrate; forming a masking layer with a pattern on the grid structure; etching the silicon-based substrate by taking the masking layer as a mask, so that a groove is formed in the part, in which a source / drain region is to be formed, of the silicon-based substrate; forming the stress layer in the groove; and removing the masking layer, wherein etching source gases for etching to form the groove contain He and O2, and the flow velocity of He to O2 is variational in the etching process. According to the invention, the uniformity of etching is improved through dynamically adjusting the flow velocity of source gases for etching the groove thereby improving the profile outline of the groove so as to improve the whole electrical property of the semiconductor device. In addition, the method can also be compatible with the traditional CMOS (complementary metal oxide semiconductor) manufacturing process.

Description

technical field [0001] The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device structure including a stress layer. Background technique [0002] At present, the main factor affecting the performance of field effect transistors is the mobility of carriers, where the mobility of carriers will affect the magnitude of the current in the channel. The reduction in carrier mobility in a field effect transistor not only reduces the switching speed of the transistor, but also reduces the difference in resistance between on and off. Therefore, in the development of Complementary Metal Oxide Semiconductor Field Effect Transistor (CMOSFET, CMOS for short), effectively improving carrier mobility has always been one of the key points in transistor structure design. [0003] Conventionally, the P-type metal oxide semiconductor field effect transistor (PMOSFET, referred to as PMOS) and the N...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/3065
Inventor 王新鹏韩秋华
Owner SEMICON MFG INT (SHANGHAI) CORP