Non-clock-state regression domino logic gate and related integrated circuit and estimation method

Abstract

The invention relates to a non-clock-state regression domino logic gate and a related integrated circuit and an estimation method. The non-clock-state regression domino logic gate responds to a plurality of input nodes comprising at least one state regression node, and a preset node is prearranged to a first state by a domino circuit. When the preset node is pulled to a second state, the domino circuit switches to a locking state and switches the state of an output node; and when a reset node is pulled to the first state, the domino circuit resets to the preset state and switches the output node to a preset value. When the above input node is in an estimation state, an estimation circuit pulls the preset node to a second state, and when the domino circuit is in a locking state, an enable circuit enables a reset condition. After an estimation event, if the rest condition is satisfied and the input node is not in an estimation state, a reset circuit pulls the rest node to a first state.

Description

technical field [0001] The present invention relates to logic circuits, and more particularly to a self-resetting return to state (RTS) domino logic gate, which operates independently of a clock signal and is used in response to a return to state (RTS) signal . Background technique [0002] The arrangement of logic circuits on an integrated circuit (IC) is usually aimed at performing logic operations quickly, and therefore, there are many possible layouts. In many instances, it is difficult and impractical to direct clock signals to circuits that provide logic operations. Including static and dynamic logic gates and circuits, most logic circuits need to operate according to an input clock. Static CMOS logic gates operate at relatively low energy, but have considerable input capacitance, and in which signals are derived from complementary P-type devices and N-type devices wrestling with each other, therefore, Static CMOS The operation of semiconductor logic gates is rather...

AI Technical Summary

Problems solved by technology

Static CMOS logic gates operate at relatively low energy, but have considerable input capacitance, and where signals are derived from complementary P-type devices and N-type devices wrestling with each other, therefore, Static CMOS The operation of semiconductor logic gates is rather slow

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