Flow method for automatically verifying correctness of electric rule file

An automatic verification and correctness technology, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve problems such as heavy workload, waste of resources, and long development time

Inactive Publication Date: 2012-03-07
MIRCOSCAPE TECH
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Problems solved by technology

Therefore, the development time of the verification process of electrical rule files commonly used in the industry is long and the workload is heavy, resulting in a lot of waste of resources

Method used

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  • Flow method for automatically verifying correctness of electric rule file

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Embodiment Construction

[0068] Step 1: Draw the layout according to the schematic diagram of the complex device model to generate a standard device layout. Export all standard layout device library cells as a data file, namely sample gds. The drawing of the standard device layout only needs to ensure the correct topological relationship of the graph, and does not need to draw the precise value of the device parameters.

[0069] Step 2: Write the parameter rule constraint file to define the specific parameter constraint principle of each device.

[0070] Step 3: call the computer software program proposed by the present invention to automatically generate layout test vectors and schematic netlists, automatically verify and generate corresponding analysis and comparison results. According to the analysis and comparison results, corresponding adjustments and corrections are made to the electrical process rule files.

[0071] For multiple devices under a typical bd1u process, we use the above steps to ...

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Abstract

The invention discloses a method for automatically generating a device test vector and a schematic diagram net list corresponding to the device test vector and automatically performing consistency check and error analysis of a layout and a schematic diagram, namely an optimization method for increasing the verification efficiency of an electric rule file in an integrated circuit aided design software tool, and belongs to the field of the consistency verification of the layout and the schematic diagram in the integrated circuit aided design software tool. The conventional manual layout drawing, schematic diagram test vector, one-by-one net list extraction and one-by-one manual verification of the correctness of the electric rule file have large flow workload and long development time and require that engineers have better design capacity and integrally master the verification flow of a process rule file better, so that the design threshold is high, and the development period is long. The invention provides a flow method for automatically verifying the correctness of the electric rule file. Compared with the conventional manual drawing, comparison and result analysis flows in the industry, the method is easy to operate, the development efficiency is greatly increased, and subsequent frequent amendment and maintenance are facilitated.

Description

technical field [0001] Automatically generate device test vectors and their corresponding schematic netlists, and automatically perform layout and schematic Figure 1 The method of consistency checking and error statistics is an optimization method for improving the verification efficiency of electrical rule files (abbreviation: LVS files) in integrated circuit aided design software tools. The invention belongs to layout and principle in integrated circuit aided design software tools Figure 1 field of consistency verification. Background technique [0002] PDK (Process Design Kit) is a data platform connecting IC design and IC process manufacturing. With the increasing complexity of integrated circuit design, it is very important to develop a process design toolkit and establish a verification reference flow to reduce the market risk caused by expensive design iterations. The electrical rule file (LVS) is one of the key components of the process design toolkit, which is cu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 张萍侯劲松王勇李宁
Owner MIRCOSCAPE TECH
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