Generation method and device of qualified crystal grain distribution pattern

A distribution map and grain technology, applied in the direction of measuring devices, instruments, semiconductor/solid-state device testing/measurement, etc., can solve problems such as errors, inaccurate qualified grain distribution maps, and affecting wafer shipment efficiency, etc., to achieve reduction The effect of manual operation, improving efficiency and accuracy

Active Publication Date: 2012-03-14
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology

In the existing technology, in order to combine the results of wafer probe testing and defect detection, a large amount of manual calibration and inspection work is required. On the one hand, this greatly affects the wafer shipment efficiency. On the other hand, manual intervention may introduce error, the obtained qualified grain distribution map may not be accurate

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  • Generation method and device of qualified crystal grain distribution pattern
  • Generation method and device of qualified crystal grain distribution pattern
  • Generation method and device of qualified crystal grain distribution pattern

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Embodiment Construction

[0037] figure 1 Shown is the generation process of the qualified grain distribution diagram proposed by the embodiment of the present invention, including the following steps:

[0038] Step 101: Obtain probe test results and defect detection results for the same wafer.

[0039] The probe test results include N1 sets of data, and N1 is the total number of dies on the wafer subjected to probe test. Each set of data includes an x ​​coordinate value and a y coordinate value, which are used to indicate the position of the crystal grain corresponding to the set of data on the wafer; the data also includes an indicator value (flag), which is used to indicate the corresponding Whether the die is qualified, for example, a logic 1 is used to indicate that it is not qualified, and a logic 0 is used to indicate that it is qualified. The defect detection result includes N2 sets of data, and N2 is the total number of crystal grains for which defect detection is performed on the wafer. Ea...

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Abstract

The invention provides a generation method of a qualified crystal grain distribution pattern. The generation method comprises the following steps of: obtaining a probe test result and a defect detection result of the same wafer; arranging a third coordinate system, defining a probe test result distribution region of the crystal grains in the third coordinate system and converting the defect detection result into the third coordinate system; with regard to a coordinate position of each crystal grain in the third coordinate system, carrying out logical operation on an indication value of a probe test and an indication value of a defect detection to obtain a final indication value of the coordinate position; determining a display way of the grain crystal according to the final indication value of each crystal grain on the wafer and generating the qualified crystal grain distribution pattern. The invention also provides a generation device of the qualified crystal grain distribution pattern. According to the scheme provided by the invention, the manual operation can be reduced to a large extent, and efficiency and accuracy of the wafer test and delivery are greatly improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a method and device for generating a qualified grain distribution map. Background technique [0002] In the final stages of wafer fabrication, each die on the wafer is sorted and tested to find defective die. If a defect is found, the defective die will be excluded based on the test data, and the qualified die will be sent to the subsequent assembly and packaging department; and the cause of the defect will be analyzed to correct the problems in the silicon wafer manufacturing process. [0003] The sorting test of the die usually includes two types: one is the probe test, which uses the probe to measure the electrical parameters of each die on the wafer one by one, and marks the state of each die according to the electrical parameters (qualified or defective) ; The other is defect detection, which detects the distribution of defects on the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/66G01B21/00
Inventor 牛海军胡亚杰魏红生
Owner SEMICON MFG INT (SHANGHAI) CORP
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