Single event upset resistant synchronously resettable D flip-flop

An anti-single-event, trigger technology, applied in the direction of electrical pulse generator circuits, pulse generation, electrical components, etc., can solve the problem of low anti-single-event flipping ability, and achieve the effect of improving the anti-single-event flipping ability.
CN102394598AActive Publication Date: 2012-03-28NAT UNIV OF DEFENSE TECH
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Patent Information

Authority / Receiving Office
CN Β· China
Current Assignee / Owner
NAT UNIV OF DEFENSE TECH
Publication Date
2012-03-28

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Abstract

The invention discloses a single event upset resistant synchronously resettable D flip-flop, aiming at improving the single event upset resistance of a resettable D flip-flop. The D flip-flop is composed of a clock circuit, a master latch, a slave latch, a first inverter circuit and a second inverter circuit, wherein the master latch is composed of 12 PMOS (P-channel Metal Oxide Semiconductor) FETs (Field Effect Transistors) and 12 NMOS (N-channel Metal Oxide Semiconductor) FETs, the slave latch is composed of 10 PMOS FETs and 10 NMOS FETs, duplication redundant reinforcement is performed on the master latch and the slave latch, and the C2MOS (Clocked Complementary Metal Oxide Semiconductor) circuit structures of the master latch and the slave latch are improved, i.e. a pull-up circuit and a pull-down circuit in the mutually redundant C2MOS circuits are separated from the master latch, and a pull-up PMOS FET and a pull-down NMOS FET in the mutually redundant C2MOS circuits are separated from the slave latch. The single event upset resistant resettable D flip-flop disclosed by the invention has strong single event upset resistance, is suitable for a standard cell library of a single event upset resistance reinforced integrated circuit, and is applied to the fields of aviation, aerospace and the like.
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Description

technical field

[0001] The invention relates to a master-slave D flip-flop with a synchronous reset structure, in particular to a synchronously resettable D flip-flop resistant to single event upset (signal event upset). Background technique

[0002] In cosmic space, there are a large number of high-energy particles (protons, electrons, heavy ions) and charged particles. After the integrated circuit is bombarded by these high-energy particles and charged particles, an electronic pulse will be generated in the integrated circuit, which may cause the original level of the internal node of the integrated circuit to flip. This effect is called single event upset (SEU). The higher the LET (Linear Energy Transfer) value of a single event bombarding an IC, the stronger the resulting electron pulse. Integrated circuits used in aviation and aerospace fields are threatened by single event upsets, which can make integrated circuits work unstable and even cause fatal errors. Therefore,...

Claims

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