Integrated circuit package with reduced parasitic loop inductance

Abstract

A multi-layer integrated circuit package includes a switched-mode power supply circuit including a plurality of transistors which form part of a main current loop of the switched-mode power supply circuit. The plurality of transistors are arranged in one or more layers of the integrated circuit package. The package further includes a conductive plate arranged in a different layer of the integrated circuit package than the plurality of transistors. The conductive plate is in close enough proximity to at least part of the main current loop so that a current can be electromagnetically induced in the conductive plate responsive to a change in current in the main current loop.

Description

technical field [0001] The present invention relates to the field of integrated circuit packaging, and in particular to an integrated circuit package with reduced parasitic loop inductance. Background technique [0002] A switch-mode power supply circuit such as a synchronous buck converter supplies power to a load through components such as capacitors, inductors, transformers, etc., and uses switches that operate in an on or off state. The switch-mode power supply circuit consumes very little power in either state, and power conversion is accomplished with minimal power loss, thus yielding high efficiency. Switched mode power supplies typically use semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). For example, a switched mode power supply may include a capacitor, an inductor, a MOSFET and a diode or alternatively a high side MOSFET and a low side MOSFET. Other component configurations are possible. In each case, components such a...

AI Technical Summary

Problems solved by technology

Parasitic inductance of critical loops limits the switching frequency of switch-mode power supply circuits

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