Semiconductor device with super junction and manufacturing method of semiconductor device
A device manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems affecting device withstand voltage stability and reliability, achieve uniform impurity concentration and distribution, and enhance reliability , uniform effect
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Embodiment 1
[0047] Such as figure 1 As shown: on the top view plane of the semiconductor device, the element region 1 includes a P column 3 and an N column 4, and the adjacent P column 3 and N column 4 form a PN column pair of a super junction structure, and the element area 1 includes multiple pairs of PN column pairs arranged in parallel; the element area 1 also includes conductive polysilicon 5 , and the conductive polysilicon 5 is located in the area corresponding to the N column 4 and is located above the N column 4 . figure 1 The peripheral area 2 is highlighted in , and the effectiveness of this embodiment is illustrated by highlighting the relationship between the PN column pairs in the peripheral area 2 and the PN column pairs in the element area 1 .
[0048] On the top view plane of the semiconductor device, the peripheral area 2 includes a first area 17 parallel to the PN column pair in the element area 1 and a second area 18 perpendicular to the PN column pair in the element a...
Embodiment 2
[0054] Such as image 3 As shown: on the top view plane of the semiconductor device, the element region 1 includes a P column 3 and an N column 4, and the adjacent P column 3 and N column 4 form a PN column pair of a super junction structure, and the element area 1 includes multiple pairs of PN column pairs arranged in parallel; the element area 1 also includes conductive polysilicon 5 , and the conductive polysilicon 5 is located in the area corresponding to the N column 4 and is located above the N column 4 .
[0055] On the top view plane of the semiconductor device, the peripheral area 2 includes a first area 17 parallel to the PN column pair in the element area 1 and a second area 18 perpendicular to the PN column pair in the element area 1, the first Both the region 17 and the second region 18 are provided with a super junction structure; the first region 17 and the second region 18 are connected end-to-end in order to form a structure surrounding the device region 1 . ...
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