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Eight-bit binary addition counter based on reversible primary and secondary D triggers

A binary addition and flip-flop technology, applied in the direction of synchronous pulse counters, etc., can solve the problems of energy loss, low-power circuit design can not be ignored, limit chip performance and calculation speed, etc., to reduce power consumption.

Inactive Publication Date: 2012-04-25
NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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Problems solved by technology

However, traditional counters are constructed of traditional logic gates, which cause erasure of information bits when performing irreversible calculations, which inevitably leads to energy loss.
[0003] Landauer pointed out that the source of energy loss in traditional irreversible logic circuits is the loss of information bits, and the loss of each bit of information corresponds to the heat generation of KT*Ln2 Joules, where K is the Boltzmann constant and T is the absolute temperature. At room temperature, Although the loss of energy is very small, it cannot be ignored for low-power circuit design
At the same time, the heat generated by energy consumption will greatly limit the performance and computing speed of the chip

Method used

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  • Eight-bit binary addition counter based on reversible primary and secondary D triggers
  • Eight-bit binary addition counter based on reversible primary and secondary D triggers
  • Eight-bit binary addition counter based on reversible primary and secondary D triggers

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Embodiment Construction

[0018] The technical solutions of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0019] Such as Figure 5 As shown, the present invention provides an eight-bit binary addition counter based on reversible master-slave D flip-flops, including 8 reversible master-slave D flip-flops and 7 FG gates for replicating signals, wherein, Figure 4b Shown is a structural schematic diagram of a reversible master-slave D flip-flop, which has two input terminals (D input terminal and CLK input terminal) and two output terminals (positive output terminal and negative output terminal), and figure 2 Shown is a schematic diagram of the structure of the FG gate, which has two input terminals and two output terminals, and its logical relationship is: set the first and second input terminals to input signals A and B respectively, and the first and second output terminals to output signals respectively P and Q, then:

[0020] P=A

[0021]...

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Abstract

The invention discloses an eight-bit binary addition counter based on reversible primary and secondary D triggers, comprising eight reversible primary and secondary D triggers and seven FGs (Forward Gates) used for copying signals. According to the structure, the energy loss problem caused by losing of information bits in the operation of irreversible circuits can be solved, and the power consumption of the circuit is greatly reduced.

Description

technical field [0001] The invention relates to the design of low-power sequential logic circuit in the information field, in particular to an eight-bit binary addition counter based on a reversible master-slave D flip-flop. Background technique [0002] The counter is widely used. It can not only be used to count the number of clock pulses, but also can be used for frequency division, timing, and beat pulse generation to meet the needs of digital measurement, calculation, program control, event statistics, and system timing. needs. However, traditional counters are constructed of traditional logic gates, which cause erasure of information bits when performing irreversible calculations, which inevitably leads to energy loss. [0003] Landauer pointed out that the source of energy loss in traditional irreversible logic circuits is the loss of information bits, and the loss of each bit of information corresponds to the heat generation of KT*Ln2 joules, where K is the Boltzman...

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Application Information

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IPC IPC(8): H03K23/50
Inventor 王友仁周影辉张培喜张砦
Owner NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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