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MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof

A technology of MOS transistor and manufacturing method, which is applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of slow system operation speed and high system power consumption, etc. large width effect

Active Publication Date: 2012-05-09
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0010] In practice, it is found that the MOS transistors produced by the existing

Method used

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  • MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof
  • MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof
  • MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof

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Embodiment Construction

[0040] When the MOS transistor manufactured in the prior art is applied to a system, the working speed of the system is relatively slow, and the power consumption of the system is large. After the research of the inventors, it is found that the operating speed of the system is slow due to the large RC time constant of the transistors manufactured in the prior art; and the high power consumption of the system is caused by the large leakage current of the transistors manufactured in the prior art. The inventor further researched and found that the reason for the large RC time constant and large leakage current of the transistor is that the source / drain junction capacitance and junction leakage current of the transistor manufactured in the prior art are relatively large.

[0041] The inventors also found that with the reduction of device feature size, it is necessary to reduce the depth of the source / drain region to form an ultra-shallow junction. This requires lower source / drain...

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PUM

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Abstract

The invention provides a MOS (Metal Oxide Semiconductor) transistor and a manufacturing method thereof; the manufacturing method comprises the following steps of: providing a semiconductor substrate, and forming a grid electrode structure on the semiconductor substrate; forming side walls on the semiconductor substrate at the two sides of the grid electrode structure; forming source/drain regions in the grid electrode structure and the semiconductor substrate at the two sides of the side walls; forming source/drain inversion regions at the bottoms of the source/drain regions, wherein conductive types of doping ions of the source/drain inversion regions are opposite to conductive types of doping ions of the source/drain regions; and annealing, and activating the doping ions of the source/drain regions and the source/drain inversion regions. The manufacturing method provided by the invention is more suitable for an ultra shallow junction manufacturing technology; and according to the manufacturing method, the junction capacitance and the junction leakage current of the MOS transistor are reduced, the response speed of a system is increased when the transistor is applied to a system, and the power consumption of the system is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for manufacturing transistors. Background technique [0002] Metal-oxide-semiconductor (MOS) transistors are the most basic devices in semiconductor manufacturing. They are widely used in various integrated circuits. According to the main carrier and the type of doping during manufacturing, they are divided into NMOS and PMOS transistors. [0003] The prior art provides a method for manufacturing a MOS transistor. Please refer to Figure 1 to Figure 3 , is a schematic cross-sectional structure diagram of a manufacturing method of a MOS transistor in the prior art. [0004] Please refer to figure 1 A semiconductor substrate 100 is provided, and isolation structures 102 are formed in the semiconductor substrate 100, the semiconductor substrate 100 between the isolation structures 102 is an active region, and a doped well 101 is formed in the active region. [00...

Claims

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Application Information

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IPC IPC(8): H01L21/336H01L29/78H01L29/06
Inventor 赵猛
Owner SEMICON MFG INT (SHANGHAI) CORP