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Buried layer N-type well-based heterojunction 1T-DRAM (one transistor dynamic random access memory) and preparation method thereof

A 1T-DRAM, heterojunction technology, applied in semiconductor/solid-state device manufacturing, electrical components, transistors, etc., can solve problems such as hole loss, achieve larger signal current, increase signal margin, and increase variation range Effect

Active Publication Date: 2012-05-09
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] 2. When the 1T-DRAM is working, the buried N-type well needs to be connected to a positive voltage to reverse the PN junction formed by the P-type body region and the buried N-type well, but it must have a PN junction reverse bias current , resulting in the loss of holes accumulated in the body region, therefore, it is necessary to minimize the reverse bias current

Method used

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  • Buried layer N-type well-based heterojunction 1T-DRAM (one transistor dynamic random access memory) and preparation method thereof
  • Buried layer N-type well-based heterojunction 1T-DRAM (one transistor dynamic random access memory) and preparation method thereof
  • Buried layer N-type well-based heterojunction 1T-DRAM (one transistor dynamic random access memory) and preparation method thereof

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Experimental program
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Effect test

Embodiment 1

[0052] refer to Figure 1~Figure 10 In this embodiment, the method for preparing a heterojunction 1T-DRAM structure based on a buried N-type well is as follows:

[0053] step 1

[0054] refer to figure 1 , provide a P-type silicon substrate 1, epitaxially layer an N-type silicon carbide layer (N-type well) 2 on the silicon substrate 1, wherein the thickness of the N-type silicon carbide layer 2 is ≥ 10nm, and the molar content of carbon is 0.01%~ 10%.

[0055] A P-type silicon layer (body region layer) 3 is epitaxially formed on the N-type well 2, and the thickness of the body region layer 3 is greater than or equal to 30 nm.

[0056] step 2

[0057] refer to figure 2 , form a shallow trench (STI) 4 on the substrate, and the shallow trench 4 is formed in the body region layer 3 and the buried layer N-type 2 well, wherein the bottom of the shallow trench 4 must be lower than the upper surface of the N-type well 2 , but higher than the lower surface of the N-type wel...

Embodiment 2

[0074] step 1

[0075] refer to figure 1 .

[0076] Provide a P-type silicon substrate, perform N-type well ion implantation and C ion implantation on the silicon substrate, and form a silicon carbide layer in the middle of the silicon substrate 1. The upper part of the silicon carbide layer is a P-type silicon layer, and the lower part is a P-type silicon layer. Silicon substrate.

[0077] Preferably, the thickness of the silicon carbide layer 2 is ≥10 nm, and the molar content of carbon is 0.01%~10%. Annealing, activating and implanting impurities to form a buried N-type well 2; the thickness of the upper P-type silicon layer is ≥30nm.

[0078] The upper P-type silicon layer is the body region layer 3, the lower P-type silicon layer is the base 1, and the middle silicon carbide layer is the N-type well 2, forming a substrate.

[0079] step 2

[0080] refer to figure 2 , determine the gate position, form a shallow trench (STI) 4 on both sides of the gate position,...

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Abstract

The invention provides a buried layer N-type well-based heterojunction 1T-DRAM (one transistor dynamic random access memory) and a preparation method thereof. A buried N-type well and a source region adopt a wide-forbidden-band semiconductor material, and a drain region adopts a narrow-forbidden-band semiconductor material, namely, performances of the conventional 1T-DRAM are improved by adopting a heterojunction method, a signal margin and the reading-writing speed of the 1T-DRAM unit are increased, the retention time of the 1T-DRAM is prolonged.

Description

technical field [0001] The invention relates to a 1T-DRAM structure, in particular to a heterojunction 1T-DRAM structure based on a buried layer N-type well and a preparation method thereof. Background technique [0002] With the continuous shrinking of the feature size of semiconductor integrated circuit devices, in order to obtain sufficient storage capacitance (generally 30fF / cell) for traditional 1T / 1C embedded DRAM cells, the capacitor preparation process (stack capacitor or deep-trench capacitor) will become more and more complicated. It is becoming more and more complex, and the process compatibility with logic devices is getting worse and worse. Therefore, Capacitorless DRAM (Capacitorless DRAM) with good compatibility with logic devices will have a good development prospect in the field of high-performance embedded DRAM in VLSI. Among them, 1T-DRAM (one transistor dynamic random access memory) has only 4F due to its cell size 2 And it has become a research hotspot...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/12H01L27/108H01L21/8242H10B12/00
Inventor 黄晓橹陈玉文
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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