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Heterojunction 1T-DRAM (dynamic random access memory) structure on basis of buried-layer N-type trap and manufacturing method of 1T-DRAM structure

A 1T-DRAM, heterojunction technology, used in semiconductor/solid-state device manufacturing, electrical components, transistors, etc., can solve problems such as hole loss, increase generation rate, increase read and write rate, and increase signal margin. degree of effect

Active Publication Date: 2015-06-17
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] 2. When the 1T-DRAM is working, the buried N-type well needs to be connected to a positive voltage to reverse the PN junction formed by the P-type body region and the buried N-type well, but it must have a PN junction reverse bias current , resulting in the loss of holes accumulated in the body region, therefore, it is necessary to minimize the reverse bias current

Method used

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  • Heterojunction 1T-DRAM (dynamic random access memory) structure on basis of buried-layer N-type trap and manufacturing method of 1T-DRAM structure
  • Heterojunction 1T-DRAM (dynamic random access memory) structure on basis of buried-layer N-type trap and manufacturing method of 1T-DRAM structure
  • Heterojunction 1T-DRAM (dynamic random access memory) structure on basis of buried-layer N-type trap and manufacturing method of 1T-DRAM structure

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0037] Referring to Figure 1, the method for preparing a heterojunction 1T-DRAM structure based on a buried N-type well in this embodiment is as follows:

[0038] step 1

[0039] refer to Figure 1A A P-type silicon substrate 1 is provided, and an N-type silicon carbide layer (N-type well) 2 is epitaxially formed on the silicon substrate 1 . Preferably, the thickness of the N-type silicon carbide layer 2 is ≥10 nm, and the molar content of carbon is 0.01%~10%.

[0040] A P-type silicon germanium layer (body region layer) 3 is epitaxially formed on the N-type silicon carbide layer. Preferably, the molar content of germanium is 0.1%~100%. When the molar content of germanium is 100%, it is a pure Ge layer; the thickness of the P-type germanium silicon layer 3 is ≥30nm.

[0041] Due to GeO 2 instability, a thin P-type Si layer 4 can also be epitaxially formed on the P-type SiGe layer 3 .

[0042] step 2

[0043] refer to Figure 1B , determine the gate position, form a ...

Embodiment 2

[0052] Referring to FIG. 2, the method for preparing a heterojunction 1T-DRAM structure based on a buried N-type well in this embodiment is as follows:

[0053] step 1

[0054] Step 1 is implemented with reference to step 1 in Example 1.

[0055] step 2

[0056] Step 2 is implemented with reference to step 2 in Example 1, but the difference is:

[0057] While preparing the gate 6, perform the LDD process to form two doped regions 62 between the shallow trenches 5, and the two doped regions 62 respectively extend from the shallow trenches 5 to the bottom of the gate 6, but are not connected. .

[0058] Then the gate sidewall 8 is formed, and the preparation process of the sidewall can be implemented with reference to the prior art.

[0059] step 3

[0060] refer to Figure 2B , etching the P-type silicon germanium layer (body region layer) 3 between the gate spacer 8 and the shallow trench 5 by photolithography, and opening the 1T-DRAM region window (drain, source r...

Embodiment 3

[0065] refer to image 3 In this embodiment, the method for preparing a heterojunction 1T-DRAM structure based on a buried N-type well is implemented with reference to Embodiment 2, the difference is that:

[0066] In step 2, when preparing the gate, no LDD process is required.

[0067] Compared image 3 and Figure 2D , the heterojunction 1T-DRAM structure prepared in this embodiment does not have the doped region 62 .

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Abstract

The invention provides a 1T-DRAM (dynamic random access memory) structure on the basis of a buried-layer N-type trap and a manufacturing method of the 1T-DRAM structure. The buried-layer N-type trap and a source drain area adopt wide-band-gap semiconductor materials, but a body area adopts narrow-band-gap semiconductor materials, namely, the performance of the conventional 1T-DRAM is improved through a method with heterojunction, thereby enlarging signal margins, prolonging the retention time of an 1T-DRAM, and improving the read-write rate of a 1T-DRAM unit.

Description

technical field [0001] The invention relates to a 1T-DRAM structure, in particular to a heterojunction 1T-DRAM structure based on a buried layer N-type well and a preparation method thereof. Background technique [0002] With the continuous shrinking of the feature size of semiconductor integrated circuit devices, in order to obtain sufficient storage capacitance (generally 30fF / cell) for traditional 1T / 1C embedded DRAM cells, the capacitor preparation process (stack capacitor or deep-trench capacitor) will become more and more complicated. It is becoming more and more complex, and the process compatibility with logic devices is getting worse and worse. Therefore, Capacitorless DRAM (Capacitorless DRAM) with good compatibility with logic devices will have a good development prospect in the field of high-performance embedded DRAM in VLSI. Among them, 1T-DRAM (one transistor dynamic random access memory) has only 4F due to its cell size 2 And it has become a research hotspot...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/108H01L29/06H01L21/8242H10B12/00
Inventor 黄晓橹顾经纶陈玉文
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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