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Heterojunction 1T-DRAM (One Transistor Dynamic Random Access Memory) structure based on buried layer N-type trap and preparation method thereof

A 1T-DRAM, heterojunction technology, used in semiconductor/solid-state device manufacturing, electrical components, transistors, etc., can solve problems such as hole loss, increase generation rate, increase read and write rate, and increase signal margin. degree of effect

Active Publication Date: 2015-07-22
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] 2. When the 1T-DRAM is working, the buried N-type well needs to be connected to a positive voltage to reverse the PN junction formed by the P-type body region and the buried N-type well, but it must have a PN junction reverse bias current , resulting in the loss of holes accumulated in the body region, therefore, it is necessary to minimize the reverse bias current

Method used

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  • Heterojunction 1T-DRAM (One Transistor Dynamic Random Access Memory) structure based on buried layer N-type trap and preparation method thereof
  • Heterojunction 1T-DRAM (One Transistor Dynamic Random Access Memory) structure based on buried layer N-type trap and preparation method thereof
  • Heterojunction 1T-DRAM (One Transistor Dynamic Random Access Memory) structure based on buried layer N-type trap and preparation method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0066] Referring to FIG. 1, the method for preparing the heterojunction 1T-DRAM structure based on the buried N-type well in this embodiment is as follows:

[0067] step 1

[0068] Such as Figure 1A As shown, a P-type underlying silicon 1 is provided; an N-type SiC layer 2 is epitaxially formed on a P-type silicon substrate 1, and the thickness of the N-type SiC layer 2 is ≥ 10 nm, and the molar content of C is between 0.01% and 10%; On the top of the N-type SiC layer 2, epitaxially layer a P-type SiGe layer 3, and make the thickness of the P-type SiGe layer 3 ≥ 30nm, and the molar content of Ge is between 0.1% and 100% (when the molar content of Ge is 100% , it is a pure Ge layer); finally, due to the GeO 2 Instability, a thin P-type silicon layer 4 can also be epitaxially extended above the P-type SiGe layer, and the thickness of this layer is much smaller than the aforementioned three layers.

[0069] step 2

[0070] refer to Figure 1B , prepare the shallow trench 5,...

Embodiment 2

[0090] Referring to FIG. 2, the method for preparing a heterojunction 1T-DRAM structure based on a buried N-type well in this embodiment is as follows:

[0091] step 1

[0092] Referring to the method described in Step 1 of Embodiment 1, a P-type silicon substrate 1 , an N-type SiC layer 2 , a P-type SiGe layer 3 , and a thin P-type silicon layer 4 are provided.

[0093] step 2

[0094] Referring to the method described in Step 2 of Embodiment 1, shallow trenches 5 are formed.

[0095] step 3

[0096] refer to Figure 2A , forming a gate 6 between two adjacent shallow trenches 5 . Referring to the method described in Step 3 of Embodiment 1, similarly, the gate oxide layer can also be retained as a subsequent selective epitaxial barrier layer.

[0097] Then, LDD process is performed on both sides of the gate 6 respectively, and low-energy Ge ion implantation is performed to form a shallowly doped source region 71 and a shallowly doped drain region 81 .

[0098] Side walls 6...

Embodiment 3

[0109] In the above-mentioned embodiment 1 of the present invention, the LDD process may not be implemented, but the N + ion implantation, in this case, as image 3 As shown, the heterojunction 1T-DRAM structure based on the buried N-type well prepared in this example differs from the heterojunction 1T-DRAM structure prepared in Example 1 in that there is no shallow drain region. Doped region 81.

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Abstract

The invention provides a heterojunction 1T-DRAM (One Transistor Dynamic Random Access Memory) structure based on a buried layer N-type trap and a preparation method thereof. According to the invention, hole potential barriers between a bulk and the buried layer N-type trap and between the bulk and a source region are effectively increased, thus the bulk potential variation range of a 1T-DRAM unit is effectively increased, and further the threshold voltage variation range is effectively increased, so that the read signal current increases, that is, the signal margin is increased. At the same time, as the hole potential barriers between the bulk and the buried layer N-type trap and between the bulk and the source region are effectively increased, the drain currents between the bulk and the buried layer N-type trap and between the bulk and the source region are effectively decreased, and the retention time of the 1T-DRAM is increased. In addition, as narrow bandgap SiGe is adopted as a bulk layer and a drain region, impact ionization effect is effectively increased, so as to improve bulk hole production rate and increase the read-write velocity of the 1T-DRAM unit.

Description

technical field [0001] The invention relates to a 1T-DRAM structure and a preparation method thereof, in particular to a heterojunction 1T-DRAM structure based on a buried N-type well and a preparation method thereof. Background technique [0002] With the continuous shrinking of the feature size of semiconductor integrated circuit devices, in order to obtain sufficient storage capacitance (generally 30fF / cell) for traditional 1T / 1C embedded DRAM cells, the capacitor preparation process (stack capacitor or deep-trench capacitor) will become more and more complicated. It is becoming more and more complex, and the process compatibility with logic devices is getting worse and worse. Therefore, Capacitorless DRAM (Capacitorless DRAM) with good compatibility with logic devices will have a good development prospect in the field of high-performance embedded DRAM in VLSI. Among them, 1T-DRAM (one transistor dynamic random access memory) has only 4F due to its cell size 2 And it ha...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/12H01L27/108H01L21/8242H10B12/00
Inventor 黄晓橹陈玉文
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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