Heterojunction 1T-DRAM (dynamic random access memory) structure on basis of buried-layer N-type trap and forming method of 1T-DRAM structure

Abstract

The invention provides a heterojunction 1T-DRAM (dynamic random access memory) structure on the basis of a buried-layer N-type trap. The heterojunction 1T-DRAM structure comprises a P-type silicon base, a N-type trap buried layer and a P-type silicon layer, wherein the N-type trap buried layer covers the P-type silicon base; the P-type silicon layer covers the N-type trap buried layer and is provided with a gate electrode and side walls positioned on the two sides of the gate electrode, shallow grooves are formed on the P-type silicon layer on the two sides of the gate electrode, and the bottoms of the shallow grooves are lower than the upper surface of the N-type trap buried layer and are not lower than the lower surface of the N-type trap buried layer; and the gate electrode and the shallow grooves on the two sides of the gate electrode are respectively provided with a source area and a drain area. According to the heterojunction 1T-DRAM structure on the basis of the buried-layer N-type trap, as N-type silicon carbide serves as the N-type trap buried layer, and N+ type silicon carbide serves as the source and drain areas, the cavity barriers between a body area and the N-type trap buried layer and between the body area and the source and drain areas are effectively enlarged, the variation range of bulk potential of a 1T-DRAM unit is effectively enlarged further, thus the variation range of a threshold voltage of the 1T-DRAM unit is effectively enlarged and signal margins are enlarged.

Description

technical field [0001] The invention relates to a structure of a non-capacitance DRAM, in particular to a heterojunction 1T-DRAM structure based on a buried layer N-type well and a method for forming the structure. Background technique [0002] With the continuous shrinking of the feature size of semiconductor integrated circuit devices, in order to obtain sufficient storage capacitance (generally 30fF / cell) for traditional 1T / 1C embedded DRAM cells, the capacitor preparation process (stack capacitor or deep trench capacitor) will It is becoming more and more complex, and the process compatibility with logic devices is getting worse and worse. Therefore, Capacitorless DRAM (Capacitorless DRAM) with good compatibility with logic devices will have a good development prospect in the field of high-performance embedded DRAM in VLSI. Among them, 1T-DRAM (One Transistor Dynamic Random Access Memory) is only 4F due to its cell size 2 And it has become a research hotspot of non-cap...

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Problems solved by technology

[0008] 2. When the 1T-DRAM is working, the buried N-type well needs to be connected to a positive voltage to reverse the PN junction formed by the P-type body region and the buried N-type well, but it must have a PN junction reverse bias current , resulting in the loss of holes accumulated in the body region, therefore, it is necessary to minimize the reverse bias current

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