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Circuit capable of improving matching degree of multi-path large current

A matching, high-current technology, applied in the direction of adjusting electrical variables, control/regulation systems, instruments, etc.

Active Publication Date: 2012-05-16
CRM ICBG (WUXI) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to provide a circuit that improves the matching degree of multi-channel high current, which solves the problem of mirror current and current caused by the deviation between transistors in the prior art The problem of reference current mismatch, it has the advantage of high matching degree of output current and reference current compared with the prior art

Method used

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  • Circuit capable of improving matching degree of multi-path large current
  • Circuit capable of improving matching degree of multi-path large current
  • Circuit capable of improving matching degree of multi-path large current

Examples

Experimental program
Comparison scheme
Effect test

Embodiment （ 1

[0046] A current mirror 1 is used to mirror the reference current source 4 into N mirror currents equal to the reference current of the reference current source 4, wherein N is an integer greater than 1, and the current mirror 1 can use a PMOS current mirror, and the PMOS current mirror The process deviation is small, so that the process deviation between the mirror current and the reference current of the reference current source 4 is small.

[0047] Wherein, the current mirror 1 can also use an NMOS current mirror, which can also achieve the effect of reducing the process deviation between the mirror current and the reference current of the reference current source 4 .

[0048] Figure 5 It is the control switch circuit diagram of the circuit that improves the matching degree of multi-channel high current in the present invention, please refer to Figure 5 , a current loop switching array 2, with N mirror current input terminals 21 and N circulating current output terminals...

Embodiment （ 2

[0053] The drain and gate of a second reference PMOS transistor 112 are connected to the reference current source 4; the drain and gate of a first reference PMOS transistor 111 are connected to the source of the second reference PMOS transistor 112; A mirrored PMOS transistor 113 is cascode-connected to the first reference PMOS transistor 111, and the cascode connection ensures that the drain currents of N first mirrored PMOS transistors 113 are the same; N second mirrored PMOS transistors 114 are connected to the second reference PMOS transistor 111. The PMOS transistors 112 are connected to the common gate; the drains of each first mirrored PMOS transistor 113 are connected to the source of a second mirrored PMOS transistor 114 in one-to-one correspondence, because the drain currents of the N first mirrored PMOS transistors 113 are the same, and The N second mirror image PMOS transistors 114 are connected to the second reference PMOS transistor 112 in a common gate manner, th...

Embodiment （ 3

[0057] N mirror current input terminals 21 are respectively A1, A2...An, N circulating current output terminals 22 are respectively B1, B2...Bn, any mirror current input terminal Am (wherein, 0<m≤n, and m , n are natural numbers) and each circulating current output terminal B1~Bn are connected with a control switch Kn, and there are N2 control switches Kn; each mirror current input terminal Am passes through N control switches K1, K2... Kn is connected to N circulating current output terminals B1~Bn, and any mirror current input terminal Am passes control switches K(n-m+1), K(n-m+2)...Kn, K1, K2... ...K(n-m) is connected to N circulating current output terminals B1~Bn.

[0058] N D flip-flops: D flip-flops D1, D2, D3...Dn; the output end of D flip-flop D (n-1) is connected to the input end 2411 of flip-flop Dn, and the output end of flip-flop Dn is connected to flip-flop D1 The input terminal 2411 is connected, wherein N is an integer greater than 1; the time pulse input term...

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Abstract

The invention discloses a circuit capable of improving matching degree of multi-path large current. The circuit comprises a current mirror, a current cyclically-switching array and a current chopping module. By using the circuit capable of improving matching degree of multi-path large current, the influence of deviation between transistors on matching precision in the prior art is eliminated, and a circuit which is capable of eliminating the influence of the process deviation between the transistors on the matching degree through carrying out period cycling switching on small-current image output current is provided.

Description

technical field [0001] The invention relates to a multi-channel high-current matching circuit, in particular to a circuit for improving the multi-channel high-current matching degree. Background technique [0002] figure 1 It is a CMOS multi-channel current mirror circuit in the prior art, such as figure 1 As shown, the circuit is formed by connecting a plurality of cascode-cogate transistors, and the reference current Iin is mirrored to the output Io1-Ion of each current source. Due to the poor matching performance of CMOS devices, there is a large mismatch between the output current and the reference current. Especially when the output current is large, such as tens of milliamperes, or hundreds of milliamperes, because a large driver tube is required, the center distance between the driver tubes is relatively long, which further exacerbates the output current mismatch problem. . [0003] figure 2 is a PMOS current mirror circuit in the prior art, please refer to fi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G05F3/26
Inventor 胡如波王觅王磊
Owner CRM ICBG (WUXI) CO LTD