White noise signal generator

Abstract

The invention discloses a white noise signal generator. The generator comprises a digital signal processor used for generating a noise control command and setting a noise waveform parameter according to user settings, a field programmable gate array (FPGA) used for receiving the noise control command generated by the digital signal processor and the noise waveform parameter and generating random sequence data according to the noise control command, a waveform DAC used for converting the random sequence data generated by the FPGA into a random sequence data analog signal, a parameter DAC used for converted the noise waveform parameter received by the FPGA into a noise waveform parameter analog signal, and an analog output circuit used for processing the random sequence data analog signal and the noise waveform parameter analog signal to output the noise signal.

Description

technical field [0001] The present invention relates to a signal generator, specifically a white noise signal generator. Background technique [0002] The analog white noise generator uses a noise diode as the noise source, but because the signal level generated by the noise diode is low, the amplifier circuit is required to have the characteristics of high gain, wide frequency band and linear phase, thus causing the analog white noise generator circuit Complex, and due to the influence of the environment, the aging of the device leads to the performance degradation of the analog white noise generator, the uneven distribution of the noise spectral density, and the narrow bandwidth. [0003] Such as figure 1 As shown, it is a kind of pseudo-random noise generator based on digital frequency synthesis (DDS, Direct Digital Synthesizer) disclosed by U.S. Patent No. 6,732,128. distribution etc. But there are also the following problems: the processor needs to re-download the wa...

AI Technical Summary

Problems solved by technology

But there are also the following problems: the processor needs to re-download the wavetable to the waveform memory every time according to the output type and noise distribution; the noise and other basic waves share the waveform memory, and the modulation of the noise cannot be realized; the single DDS structure, It can only realize the noise output of the clock source with a sampling rate of 200MHz, and if it is realized by FPGA, it will occupy a lot of FPGA resources

Images