Gate forming method

Abstract

The invention discloses a gate forming method comprising the following steps: providing a substrate; forming a gate dielectric layer on the surface of the substrate, forming a tungsten nitride layer on the surface of the gate dielectric layer and forming a tungsten layer on the surface of the tungsten nitride layer; patterning the tungsten nitride layer and the tungsten layer; etching part of patterned tungsten nitride layer and tungsten layer by using a wet process, and forming a false gate, wherein the speed for etching the tungsten nitride by using the wet process is larger than the speed for etching tungsten, and the false gate is T-shaped and comprises the tungsten nitride layer and the tungsten layer which are etched by using the wet process; forming a dielectric layer to cover the gate dielectric layer, wherein the surface of the dielectric layer is level with the surface of the false gate; removing the false gate to form a T-shaped gate trench; and filling gate materials in the gate trench to form a gate. The gate forming method is beneficial to filling the gate materials, and formed gaps can be avoided or at least reduced; and the method is simple, and the defect that the substrate is damaged in the prior art can be avoided.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a gate. Background technique [0002] In the prior art, the process of forming a gate can be divided into a gate first process and a gate last process. The gate-front process refers to first depositing a gate dielectric layer, forming a gate electrode on the gate dielectric layer, then performing source-drain implantation, and then performing an annealing process to activate ions in the source-drain. The process steps of the front-gate process are simple, but during annealing, the gate electrode must inevitably withstand high temperatures, resulting in a shift in the threshold voltage Vt of the MOS tube and affecting the performance of the tube. The gate last process means that after the annealing process, that is, after the high temperature step, the polysilicon dummy gate is etched away to form a dummy gate trench, and then the dummy gate trench is ...

AI Technical Summary

Problems solved by technology

However, in this patent document, the argon (Ar) sputtering process is used to increase the width of the top of the trench, which is easy to cause damage to the substrate

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