Digital burr filtering circuit for clock pins of smart card

Abstract

Disclosed is a digital burr filtering circuit for clock pins of a smart card. The burr filtering circuit which is composed by a plurality of gate circuits is added at the input end of the clock pins of the smart card, high frequency burrs on the clock pins are filtered on the promise that the duty ratio is not affected. The circuit comprises a NOND gate, a NOR gate, an inverter, a delayed component chain, and a reset-set (RS) flip-flop. According to the digital burr filtering circuit for the clock pins of the smart card, nanosecond burrs can be filtered effectively, and the problem of interference to clock pins of the smart card is solved.

Description

technical field [0001] The invention relates to a digital burr filter circuit, in particular to a digital burr filter circuit which does not affect the duty cycle in smart card applications. Background technique [0002] Nowadays, smart card applications are popular in various fields, such as public transportation, social security, identification and other fields. In order to improve the competitiveness of smart card products, the smart card chip design company continuously improves the anti-interference ability of smart cards and provides better quality products. In the anti-jamming design, improving the anti-jamming ability on the clock pin of the smart card is an important part of improving the anti-jamming ability. [0003] The clock pins used by the smart card are generally provided by the OEM of the smart card chip during chip processing. According to different foundries and different process lines, the circuit design of clock pins will be different. In general, the...

AI Technical Summary

Problems solved by technology

It can effectively filter out nanosecond glitch interference and solve the anti-interference problem of smart card clock pins

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