Negative voltage transformation circuit

Abstract

A negative voltage transformation circuit comprises a voltage clamping circuit and an output circuit. The voltage clamping circuit is connected with positive voltage and negative voltage and used for outputting clamping to the output voltage of the positive voltage or the negative voltage according to a received first input signal and a received second input signal. The output circuit is connected with the voltage clamping circuit and used for outputting voltage corresponding to the negative pressure according to the output voltage of the voltage clamping circuit. A first voltage value of the positive voltage is transformed into a second voltage value when the negative pressure drops to a preset voltage value, the second voltage value is 0V, and the first voltage value is larger than the second voltage value. The negative voltage transformation circuit effectively prevents every metal oxide semiconductor (MOS) from being broken down, thereby improving reliability of the circuit. In addition, the area of the circuit is effectively reduced so that the integration of the circuit is improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a negative voltage conversion circuit. Background technique [0002] During the operation of integrated circuits, different voltages are usually required, and the input voltage of the circuit is usually single or limited. Therefore, in the circuit design, it is necessary to convert the input voltage into different positive or negative voltages. circuit. Level conversion circuits are widely used in various interface circuits and input and output units to realize level logic conversion. [0003] figure 1 A typical negative voltage conversion circuit in the prior art is shown. Such as figure 1 As shown, the negative voltage conversion circuit includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor tube N4 and the fifth N...

AI Technical Summary

Problems solved by technology

At this time, the drain voltage of the third PMOS transistor P3 is -7V, and the source voltage is 1.8V, therefore, the voltage difference between the drain and the source of the third PMOS transistor P3 is -8.8V , this voltage difference is close to the breakdown voltage of the MOS transistor (usually the breakdown voltage of the PMOS transistor is -9V), so it is easy to cause the breakdown of the third PMOS transistor P3

[0012] on the other hand, figure 1 The forward voltage Vcg in the negative voltage conversion circuit in the circuit is 1.8V, and the external power supply in the circuit usually only provides a single voltage such as 3V, then the forward voltage Vcg needs to be realized by the voltage regulation circuit, so that Increase the area of ​​the circuit, which is not conducive to the integration of the circuit

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