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Low-power-consumption domino three-value character arithmetic circuit

An arithmetic circuit and low power consumption technology, which is applied in the field of low-power domino three-valued word operation circuit, can solve the problems of less research on word operation circuits and three-value word operation circuits, and achieve low power consumption, simple structure, small area effect

Inactive Publication Date: 2012-08-01
HANGZHOU MAEN TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, compared with gate circuits such as ternary AND gates and OR gates, there are relatively few studies on ternary word operation circuits, and even less research on word operation circuits suitable for adiabatic domino circuits

Method used

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  • Low-power-consumption domino three-value character arithmetic circuit
  • Low-power-consumption domino three-value character arithmetic circuit
  • Low-power-consumption domino three-value character arithmetic circuit

Examples

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Effect test

Embodiment 1

[0018] Example one: such as figure 1 As shown, a low-power domino ternary text operation circuit includes a first text arithmetic circuit unit 1, a second text arithmetic single-channel unit 2 and a third text arithmetic circuit unit 3. The first text arithmetic circuit unit 1 is mainly composed of a first The PMOS tube P1, the second PMOS tube P2, the third PMOS tube P3, the first NMOS tube N1, the second NMOS tube N2, and the third NMOS tube N3 are composed of the source of the first PMOS tube P1 and the first NMOS tube N1. The drain is connected in parallel to the first signal output terminal, and the first signal output terminal is used to output the first output signal when the logic value is 0 0 x 0 , The source of the first NMOS tube N1 is connected to the drain of the second NMOS tube N2, the source of the second PMOS tube P2 is connected to the drain of the third PMOS tube P3, and the source of the third PMOS tube P3 is connected to the third The drain of the NMOS trans...

Embodiment 2

[0053] Embodiment two: such as Image 6 As shown, this embodiment is basically the same as the first embodiment, except that the first character operation circuit unit 1 is connected to the first waveform conversion circuit 11, the second character operation circuit unit 2 is connected to the second waveform conversion circuit 21, and the third The text operation circuit unit 3 is connected to a third waveform conversion circuit 31. The first waveform conversion circuit 11 is mainly composed of an eighth NMOS tube N8 and a ninth NMOS tube N9. The drain of the eighth NMOS tube N8 is connected to the first signal output terminal. , The source of the eighth NMOS tube N8 is connected to the gate of the ninth NMOS tube N9, the gate of the eighth NMOS tube N8 is connected to the clock signal input terminal, and the source of the ninth NMOS tube N9 is connected to the power clock signal input terminal , The drain of the ninth NMOS tube N9 is the first waveform conversion signal output ...

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Abstract

The invention discloses a low-power-consumption domino three-value character arithmetic circuit, which comprises a first character arithmetic circuit unit, a second character arithmetic circuit unit and a third character arithmetic circuit unit. The first character arithmetic circuit unit, the second character arithmetic circuit unit and the third character arithmetic circuit unit all achieve functions through a heat insulation circuit, a three-value character arithmetic circuit and a domino circuit. The low-power-consumption domino three-value character arithmetic circuit has the advantages of integrating the heat insulation circuit and the domino circuit into the three-value character arithmetic circuit, converting energy of circuits according to a sequence of a power supply-a signal node-a power supply through the heat insulation circuit, being capable of effectively reducing power consumption of the circuits, enabling the power consumption of the circuits to be low, enabling the circuits to have smaller area by combining the domino circuit with a multi-value circuit, further improving information density of the circuits, reducing the quantity of chip pins and connecting wires, and enabling the circuits to have simple structures.

Description

Technical field [0001] The invention relates to a three-valued character operation circuit, in particular to a low-power consumption domino three-valued character operation circuit. Background technique [0002] At present, semiconductor technology has entered the deep sub-micron era, and the number of transistors integrated on a single chip has been very large, and it is still growing at a rate that exceeds Moore's Law. It is expected that in 2020, the feature size of integrated circuits will reach 14 nm, which will be followed by a surge in circuit power consumption and complex circuit structure. Therefore, reducing circuit power consumption and simplifying circuit structure have become the two primary considerations for chip design. Goals. Among the many ways to achieve low power consumption, the adiabatic circuit using AC pulse power has changed the energy transmission mode of the traditional circuit, so that the energy is recycled from the power supply → the signal node → t...

Claims

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Application Information

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IPC IPC(8): H03K19/094
Inventor 汪鹏君杨乾坤郑雪松
Owner HANGZHOU MAEN TECH
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