Two-dimensional image resampling algorithm accelerator based on field-programmable gate array (FPGA)

Abstract

The invention discloses a two-dimensional image resampling algorithm accelerator based on a field-programmable gate array (FPGA). The accelerator comprises a FPGA chip and an external memory. The FPGA chip stores a known image collected externally into the external memory. During carrying out resampling processing, the FPGA chip reads data of the known image from the external memory and carries out calculating, and then stores the calculated result image into the external memory and outputs to the external. By using the accelerator of the invention, the resampling processing of the two dimensional image with rigid transformation can be realized.

Description

technical field [0001] The invention relates to the fields of digital image processing, circuits and systems, in particular to a two-dimensional image resampling algorithm accelerator. Background technique [0002] With the rapid development of image acquisition technology and application requirements, the data volume of a single image and the total image data volume per unit time are showing an exponential growth trend, thus bringing forward the processing speed of traditional software-based image applications. Great challenge. There are two main ways of traditional image processing based on software: ① stand-alone image processing software based on desktop PC computers, workstations, servers, etc.; ② multi-machine parallel image processing software based on massively parallel processors, cluster systems, etc. . From the perspective of users, method ① has the characteristics of small platform size and convenient use by users, but limited by platform performance, its proce...

AI Technical Summary

Problems solved by technology

From the perspective of users, method ① has the characteristics of small platform size and convenient use by users, but limited by platform performance, its processing speed cannot meet the real-time or timely processing requirements of modern image applications for large-scale data

Method ② has the advantages of high processing performance and strong real-time performance, but it is extremely inconvenient for ordinary users due to the low availability of large-scale parallel computing platforms and the high design difficulty of parallel algorithms

At the same time, the above two methods have a common disadvantage: poor environmental applicability, and it is difficult to meet the needs of occasions with special requirements for volume and performance (such as spaceborne remote sensing image processing)

Since the storage block capacity integrated in FPGA is usually only a few KB to several MB, which cannot meet the processing requirements of large-capacity image data, no image resampling algorithm accelerator based on FPGA chip has been found in the existing accelerator design.

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