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Level shifter design

A technology of level shifters and resistors, which is applied in the direction of electrical components, logic circuits, and generating electric pulses, and can solve problems such as damaging devices

Active Publication Date: 2012-09-19
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Without a high-voltage-tolerant output driver, device voltage limitations dictated by process technology can damage the device

Method used

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Embodiment Construction

[0034] The making and using of various embodiments of the invention are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable concepts that can be implemented in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

[0035] Exemplary embodiments of level shifter designs will be described below, implemented using NMOS transistors, PMOS transistors, inverters, and other basic logic circuits. Those skilled in the art will readily appreciate that there are many variations that can achieve equivalent functions, and these illustrative embodiments are for illustration purposes only.

[0036] Figure 1(a) shows a block diagram of an exemplary embodiment of a level shifter circuit. The circuit comprises a first inverter X1, an inductor C1, a resistor R1, and a latching circuit "Latch". The f...

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PUM

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Abstract

The invention relates to a level shifter design. A level shifter receives an input voltage signal and produces an output voltage signal. The level shifter includes a first inverter, configured to operate at a potential difference between a first voltage V1 and a second voltage V2. The output from the invert is capacitively coupled to an input of a latch circuit via a capacitor. The capacitor has a first terminal connected to the output terminal of the first inverter, and further has a second terminal. The level shifter has a resistor connected to a third voltage V3 and to the capacitor for tying the input to the latch circuit to a desired voltage. The latch circuit is configured to operate at a potential difference between a fourth voltage V4 and a fifth voltage V5. The latch has an input node connected to the resistor and the capacitor, and further has an output node connected to an output node of the level shifter.

Description

technical field [0001] The present invention relates generally to digital circuits and, more particularly, to level shifting circuits for converting digital signals between two different voltage levels. Background technique [0002] Field Effect Transistors (FETs, or transistors) conduct with electrons (in N-channel FETs) or holes (in P-channel FETs). The four terminals of a transistor are source, gate, drain, and body (substrate). In a transistor, the drain-source current flows through a conduction channel that connects the source region to the drain region. When a voltage (marked as V gs ), an electric field is generated, which controls the conductivity. Typically, the body terminal is connected to either the highest voltage or the lowest voltage in the circuit. Because the source terminal is sometimes connected to the highest voltage or the lowest voltage in the circuit, the body and source terminals are sometimes connected together. Typically, the input signal is ap...

Claims

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Application Information

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IPC IPC(8): H03K19/0175
CPCH03K3/037H03K19/018507
Inventor 罗许·艾伦徐英智石硕索南·艾瑞克
Owner TAIWAN SEMICON MFG CO LTD
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