Method for modeling metal oxide semiconductor (MOS) device

Abstract

The invention provides a method for modeling a metal oxide semiconductor (MOS) device. The MOS device comprises a first type of STI structure at a source end and a second type of STI structure at a drain end. The method for modeling the MOS device comprises the following steps of: a) establishing a group of parameters for defining the distance from a channel region of the device to the first type of STI structure and the distance from the channel region of the device to the second type of STI structure; b) establishing an analytical model of the group of parameters on the influence of the mobility ratio, wherein the analytical model comprises a coefficient to be determined; c) testing a first type of MOS device comprising the first type of STI structure at the source end and the drain end and a second type of MOS device comprising the second type of STI structure at the source end and the drain end, and acquiring the testing data; and d) determining the coefficient of the analytical model according to the testing data. The modeling method is simple and practicable, high in operability and wide in application range.

Description

technical field [0001] The invention relates to the field of device modeling, in particular to a method for modeling a MOS device including both a shallow trench isolation (STI, shallow trench isolation) structure and an ultra-shallow trench isolation (VSTI, very shallow trench isolation) structure. Background technique [0002] As the complexity of integrated circuit design is getting higher and higher, and the size is getting smaller and smaller, the role of isolation technology in integrated circuit manufacturing is becoming more and more important. The isolation technology under the CMOS process mainly includes dielectric material isolation and reverse PN junction isolation, among which dielectric material isolation has excellent performance in eliminating parasitic transistors, reducing working capacitance, and suppressing the latch-up effect of MOS transistors. In the 3-0.35μm process, the local oxidation (LOCOS) process is widely used, but this process has its own def...

AI Technical Summary

Problems solved by technology

In the 3-0.35μm process, the local oxidation (LOCOS) process is widely used, but this process has its own defects: (1) the bird's beak structure makes the field silicon dioxide invade the active area; (2) ) Field oxygen implantation redistributes at high temperature, causing narrow width effect of active devices; (3) Field silicon dioxide becomes thinner in narrow isolation regions; (4) Uneven surface shape

The current stress model only considers the influence of STI, and does not comprehensively consider the influence of STI and VSTI on circuit performance, so it is necessary to model this SOI MOS device by integrating the influence of STI and VSTI

Images