Formation method of metal gate

Abstract

The embodiment of the invention discloses a formation method of a metal gate, which comprises the following steps: a substrate is provided; a fake gate is formed on the surface of the substrate; an etch barrier layer is formed on the surfaces of the fake gate and the substrate; a first interlayer dielectric layer is formed on the surface of the etch barrier layer; a part of the first interlayer dielectric layer is removed, and the surface of the first interlayer dielectric layer is lower than the surface of the fake gate; after a part of the first interlayer dielectric layer is removed, an abrasive barrier layer covering the first interlayer dielectric layer is formed; the abrasive barrier layer and the etch barrier layer are flattened, and the surface of the fake gate is exposed; the fake gate is removed, and the metal gate is formed. The formation method of the metal gate can effectively solve the problems of metal residuals caused by dishing of the first dielectric layer and thickness instability of the metal gate, and the formation process is simple.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductors, and in particular to a method for forming a metal gate. Background technique [0002] Nowadays, in lower process nodes, a gate stack structure combining a gate dielectric layer of a high-k material with a low equivalent oxide thickness (EOT, Equivalent Oxide Thickness) and a metal gate electrode is widely used. [0003] The patent with the publication number CN101567335A discloses a method for fabricating a metal gate structure. First, a dummy gate is formed on the surface of the substrate, and then an interlayer dielectric layer is formed on the surface of the substrate to cover the dummy gate, and the interlayer dielectric layer is planarized to expose removing the dummy gate, then removing the dummy gate to form an opening, and then filling metal material and gate dielectric material to form a metal gate. [0004] The method for forming the metal gate in the prior art is as...

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Problems solved by technology

When the above-mentioned structure is planarized by chemical mechanical polishing, there will be problems: on the one hand, the surface of the dummy gate 103 is easily oxidized to form an oxide film, and when the oxide film is removed by wet etching in the subsequent process , the chemical reagent of wet etching will also corrode the first interlayer dielectric layer 107 at the same time, and it is easy to form small pits in the first interlayer dielectric layer 107 in the dense area of ​​dummy gates 103; gate, and when the surface of the metal gate is chemically mechanically polished, the polishing particles are easily dispersed around the metal gate, especially in the area of ​​the larger dummy gate 103, and the first interlayer dielectric layer around the larger dummy gate 103 107 is damaged, forming large pits, that is, dishing

[0011] The large and small pits will affect the semiconductor device: on the one hand, the thickness of the high-K metal gate formed subsequently is small, and the performance of the semiconductor device is unstable; on the other hand, after removing the dummy gate to form Opening, when filling metal material into the opening and performing chemical mechanical polishing, there will be metal residue in the pit of the first interlayer dielectric layer, causing a short circuit

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