Power-on reset circuit and its reset method
A reset circuit and electrical reset technology, applied in data reset devices, electronic switches, electrical components, etc., can solve the problems of high power consumption and unstable performance of the power-on reset circuit, so as to solve the problem of high power consumption and reduce design and development costs. , the effect of increasing reliability
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Embodiment 1
[0063] This embodiment provides a power-on reset circuit, which can provide a power-on reset signal (POR) for its internal circuit, and is used in a circuit that needs to start the circuit. For example, a start-up circuit for the bandgap circuit may be provided by an internal self-biasing circuit.
[0064] Figure 6 is a schematic diagram of a power-on reset circuit according to Embodiment 1 of the present invention, as shown in Figure 6 As shown, C0 is used to keep the initial voltage of rstb0 at a low potential (that is, the initial state of POR) when powering on, and the rst signal is obtained through a Schmitt inverter (INV_SMT); PM0 (that is, the switch module 208) is used to Latch POR completion state.
[0065] At the initial stage of power-on, due to the existence of C0, V_S is initially at a low level, then POR is at a high level, and the VBIAS module (that is, the self-bias module 202) is enabled to generate V_NG. When the VFB module (that is, the feedback module 2...
Embodiment 2
[0072] This embodiment provides an implementation scheme of a self-bias circuit. Figure 8It is a schematic diagram of a self-bias circuit according to Embodiment 2 of the present invention. The self-bias circuit is composed of PM0, PM1, NM0, NM1, and R0. During implementation, different cascode MOS transistors ( cascode) to change the voltage value of V_NG; PM4 and C1 are used to start the self-bias circuit; PM3, NM4 and I9 are used to close the self-bias circuit after startup (for example, EN is a high active enable signal); NM3 is used for Short the negative node of C1 to ground after the startup is complete.
[0073] After power-on, in the fast rising or falling stage, the internal working voltage VDD may drop sharply. If the capacitor C1 is directly coupled to the self-bias circuit, the self-bias circuit may be turned off at this time. However, in this embodiment PM4 (ie, protection module 302) is used to avoid this from happening. When the POR is still in the initial s...
Embodiment 3
[0079] Figure 9 is a schematic diagram of a start-up circuit providing a controlled node voltage according to Embodiment 3 of the present invention, as shown in Figure 9 As shown, the controlled node voltage V_FB of the power-on reset circuit in this embodiment (that is, V FG ) can come from but not limited to the following ways: (a) VDD resistor divider, that is, a resistor divider that senses the VDD level; (b) current source charging, which can be charged by a capacitor to obtain a delayed current source; (c) External other reference feedback, POR itself has no power consumption (but other references have power consumption), for example, the output of the bandgap circuit. Alternatively, V_FB can come from any node whose final steady-state voltage is higher than the internal V_NG voltage value (to complete power-on-reset).
[0080] For example, the start-up circuit at the controlled node voltage (ie, the output voltage V_FB of the feedback module 204) is Figure 9 In (a...
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