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Asynchronous FIFO (first in first out) address conversion circuit based on Lee restricting competition counting coding

An address conversion circuit, a technology that restricts competition counting, applied in the field of microelectronics, can solve problems such as clock crossing, save resources, facilitate address management, and produce convenient effects

Active Publication Date: 2012-11-28
SOUTHEAST UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Both read and write addresses are multiple bits wide, so direct clock crossing won't solve the problem

Method used

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  • Asynchronous FIFO (first in first out) address conversion circuit based on Lee restricting competition counting coding
  • Asynchronous FIFO (first in first out) address conversion circuit based on Lee restricting competition counting coding
  • Asynchronous FIFO (first in first out) address conversion circuit based on Lee restricting competition counting coding

Examples

Experimental program
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Embodiment Construction

[0042] Below in conjunction with accompanying drawing, technical scheme of the present invention is described in further detail:

[0043] like figure 2 As shown, the present invention has designed a kind of asynchronous FIFO address conversion circuit based on Lee's restricted competition counting code, including write logic circuit based on Lee's code, read logic circuit based on Lee's code, write address to read clock domain logic circuit And read address to write clock domain logic circuit, described write logic circuit based on Lee's code comprises asynchronous FIFO write address generation circuit, first Lee's code turn BCD code circuit and first read and write address comparison logic circuit, described based on The read logic circuit of Lee's encoding includes an asynchronous FIFO read address generation circuit, a second Lee's encoding to BCD code circuit and a second read and write address comparison logic circuit, wherein:

[0044] The asynchronous FIFO write addre...

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PUM

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Abstract

The invention discloses an asynchronous FIFO (first in first out) address conversion circuit based on Lee restricting competition counting coding. The asynchronous FIFO address conversion circuit comprises a writing logic circuit based on the Lee coding, a reading logic circuit based on the Lee coding, a writing address to reading clock domain logic circuit and a reading address to writing clock domain logic circuit. By utilizing the asynchronous FIFO address conversion circuit based on the Lee restricting competition counting coding, asynchronous FIFO with the depth being 16 can be subjected to address conversion and management by the Lee restricting competition counting coding, an address generating circuit is simplified, and the reliability of the asynchronous FIFO is improved.

Description

technical field [0001] The invention relates to the technical field of microelectronics, in particular to design an asynchronous FIFO address conversion circuit based on Lee's restricted competition counting code. Background technique [0002] In a communication processing system, data transmission between different clock domains is often required. If it is multi-bit data transmission, in order to ensure data integrity during transmission between asynchronous clock domains, a common method is to use asynchronous FIFO, such as figure 1 As shown, the data enters the cache in the write clock domain and is read out in the read clock domain. In order to ensure the consistency and integrity of the data when the data cache is written and read at the same time, the write address and The relative position of the read address is logically compared to determine the status of the cache (read empty or full). [0003] Due to the asynchrony of the read clock, the address pointers for rea...

Claims

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Application Information

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IPC IPC(8): G06F5/06
Inventor 李冰章旭东
Owner SOUTHEAST UNIV
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