Display interface circuit

Abstract

The invention discloses a display interface circuit, which comprises a physical layer circuit, a picture buffer, a display serial interface, a configuration register and an asynchronous latency circuit, wherein the physical layer circuit is used for receiving an initial data signal and an initial clock signal, modulating the levels of the initial data signal and the initial clock signal and respectively generating a data signal and a clock signal; the picture buffer is used for storing and outputting the data signal according to an instruction signal of the clock signal; the display serial interface is used for transmitting the data signal and the clock signal through a data packet; the configuration register is used for generating the instruction signal according to an asynchronous clock signal and the data signal; and the asynchronous latency circuit is used for adjusting a clock latency of the clock signal which is transmitted to the configuration register to generate the asynchronous clock signal.

Description

technical field [0001] The invention relates to a display interface circuit, in particular to a display interface circuit which adjusts a clock delay through an asynchronous flip-flop circuit. Background technique [0002] With the development of technology, handheld devices such as smart phones and personal digital assistants (PDAs) integrate more and more communication and display technologies to realize various application functions. In order to control various application functions at the same time, a high-speed processing interface is required between the processor and the display panel of the smart handheld device to increase the amount of data transmission, thereby improving the image quality of the panel display or touch functions. To this end, industry leaders have proposed a Mobile Industry Processor Interface (MIPI), which is used to standardize the application processor interface of handheld devices. [0003] Please refer to figure 1 , figure 1 It is a schemat...

AI Technical Summary

Problems solved by technology

However, with the demand for high-speed transmission, the oscillation rate of the clock signal CLK gradually increases, and the clock delay LTC will cause CLK_b to violate the hold time specification of the clock signal, such as Figure 2B As shown, the result will be that the mobile industry processor interface 10 will not work

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