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Semiconductor device with device terminal electrode exposed at substrate end and method for manufacturing same

A device terminal and semiconductor technology, applied in the field of semiconductor device structure, can solve the problems of cumbersome process and cost

Active Publication Date: 2015-08-26
ALPHA & OMEGA SEMICON INT LP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Despite the above advantages, the independence of TSVs, and the associated fabrication steps on the backside of the thinned wafer, still bring unnecessary tediousness and expense to the process.

Method used

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  • Semiconductor device with device terminal electrode exposed at substrate end and method for manufacturing same
  • Semiconductor device with device terminal electrode exposed at substrate end and method for manufacturing same
  • Semiconductor device with device terminal electrode exposed at substrate end and method for manufacturing same

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Embodiment Construction

[0071] The above and following description and drawings are included herein to illustrate only one or more presently preferred embodiments of the invention, as well as some typical alternatives and / or alternative embodiments. The description and drawings are for purposes of illustration and, as such, do not limit the invention. Accordingly, various alterations, changes, and modifications will readily occur to those skilled in the art. These alterations, changes and amendments should also be considered to belong to the scope of the present invention.

[0072] Figure 1C Shows a cross-sectional view of a prior art bottom drain power MOSFET device 1 with an active portion 1a and a gate interconnect portion 1b on a semiconductor substrate with a bottom drain metal layer 22 ( SCS) above 21. The active portion 1 a has a plurality of spaced apart source-body regions 23 and trenched gate regions 24 within a semiconductor device region (SDR) 3 of a semiconductor substrate 21 , all o...

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PUM

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Abstract

The innovation comprises a semiconductor device with a device-side electrode exposed at a substrate end (SEDE). The semiconductor device is provided with a semiconductor substrate (SCS) with a device side, a substrate end and a semiconductor device region (SDR) arranged at the device side. In order to run the device, the device-side electrode (DSE) is formed. A through substrate groove (TST) penetrates through a semiconductor substrate to extend and touch the device-side electrode so as to be changed into the device-side electrode exposed at the substrate end. Electric connecting wires penetrate through the through substrate groove to mutually connect with the device-side electrode exposed at the substrate end. The device-side electrode can further comprise an extended support frame which is stacked under the device-side electrode exposed at the substrate end, so that the structure support can be conveniently provided for the device-side electrode when a wafer is packed.

Description

technical field [0001] The present invention generally relates to the field of semiconductor device structures. More specifically, the present invention relates to device structures and methods for preparing power semiconductor devices, such as power metal-oxide-semiconductor field effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs), which simplify wafer post-processing . Background technique [0002] For system-in-packages of power MOSFET devices, bottom-source power MOSFETs are sometimes required to optimize chip layout and / or reduce package-related parasitic interconnect impedances. One such example is presented in US application 11 / 830951, which proposes a multi-die semiconductor package for a DC-DC booster converter, having a lead frame with a grounded die pad; a bottom-source N-channel MOSFET; and an anode-substrate Schottky diode with its anode connected to the drain of the vertical MOSFET. The Schottky diode chip and the vertical MOSFET chi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/417H01L21/336
CPCH01L2924/12032H01L2224/04042H01L2224/48463H01L2924/13091H01L24/06H01L2224/73265H01L24/49H01L2224/48091H01L2224/02166H01L2924/13055H01L24/48H01L24/05H01L2924/1461H01L2224/49107H01L2224/48465H01L2224/48H01L2224/49H01L2924/10155H01L2924/181
Inventor 冯涛安荷·叭剌
Owner ALPHA & OMEGA SEMICON INT LP
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