Method of forming a multi-gate device

Abstract

The invention discloses a method for forming a multi-gate device. The method includes that a semiconductor substrate is provided, a protruding fin portion is formed on the semiconductor substrate, a dielectric layer and a sacrificial layer are sequentially formed, the dielectric layer covers the semiconductor substrate and the fin portion, the sacrificial layer covers the dielectric layer, the sacrificial layer is subjected to a first reactive ion etching until the dielectric layer is exposed, the residual sacrificial layer and the dielectric layer are subjected to a second reactive ion etching, the sacrificial layer is completely removed, a part of the dielectric layer is removed, etching rate of the second reactive ion etching on the sacrificial layer is smaller than that of the second reactive ion etching on the dielectric layer, and the residual dielectric layer is subjected to a third reactive ion etching so as to expose the top and a part of side wall of the fin portion. The method has the advantages that the improvement of the overall and partial flatness of the dielectric layer can be facilitated, and the consistency of the device is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a multi-gate device. Background technique [0002] With the continuous development of semiconductor process technology, under the 45nm and 32nm process nodes, the gate-last process has been widely used to obtain an ideal threshold voltage and improve device performance. However, when the feature size (CD, Critical Dimension) of the device is further reduced, even if the gate-last process is adopted, the structure of the conventional MOS field effect transistor can no longer meet the requirements for device performance, and multi-gate devices have been widely used as a substitute for conventional devices. s concern. [0003] Fin field effect transistor (FinFET) is a common multi-gate device, figure 1 A schematic diagram of a three-dimensional structure of a fin field effect transistor in the prior art is shown. Such as figure 1 As shown, it includes...

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Problems solved by technology

However, still referring to Image 6 , in the prior art, chemical mechanical polishing is often used to planarize the surface of the dielectric layer 22, and the local flatness of the final dielectric layer 22 is relatively poor, so after the dielectric layer 22 is etched, the final remaining part of the dielectric layer 22 The uniformity of thickness is poor, which affects the consistency of parameters among multiple multi-gate devices formed

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