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Semiconductor structure and manufacturing method thereof

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of reduced semiconductor drive current, difficulty in reducing semiconductor structure, and limitations.

Active Publication Date: 2013-01-02
BEIJING NAURA MICROELECTRONICS EQUIP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, reducing the width of the source / drain region will directly lead to a reduction in semiconductor drive current and a decrease in semiconductor performance
According to the traditional semiconductor process, since a contact plug needs to be formed on the source / drain region, the design of the length of the source / drain region is limited by the length of the contact plug
These two limitations make it difficult to reduce the area of ​​the source / drain region. Correspondingly, it is difficult to reduce the semiconductor structure and increase the integration of semiconductor devices.

Method used

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  • Semiconductor structure and manufacturing method thereof
  • Semiconductor structure and manufacturing method thereof
  • Semiconductor structure and manufacturing method thereof

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Embodiment 1

[0031] Please refer to Figure 6(a), Figure 7 , Figure 8(a) and Figure 9(a). Figure 6(a), Figure 7 , FIG. 8(a) and FIG. 9(a) are top structural schematic diagrams of various manufacturing stages according to a specific embodiment of the present invention. The semiconductor structure includes a substrate 100 , gate stacks, spacers 240 , source / drain regions 110 and source / drain epitaxial regions 120 . The gate stack is formed on the substrate 100, and the sidewall 240 is formed at the sidewall of the gate stack. After planarization, the interlayer dielectric layer 300 is flush with the tops of the source / drain region 110 and the source / drain epitaxial region 120, as shown in Figure 7 shown. A contact hole 310 penetrating through the interlayer dielectric layer 300 is formed above the source / drain epitaxial region 120 to expose the source / drain epitaxial region 120 , as shown in FIG. 8( a ). And a contact metal is filled in the contact hole 310 to form a contact plug 320,...

Embodiment 2

[0036] Please refer to Figure 6(b), Figure 7 , Figure 8(b) and Figure 9(b). Figure 6(b), Figure 7 , FIG. 8(b) and FIG. 9(b) are top structural schematic diagrams of various manufacturing stages according to another specific embodiment of the present invention. The difference from Embodiment 1 is that there are two source / drain epitaxial regions 120, contact holes 310, and contact plugs 320 on each side of the gate stack, and multiple contact plugs can make the contact resistance of the source / drain regions better. small, improving the overall performance of the device.

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PUM

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Abstract

The invention provides a semiconductor structure and a manufacturing method thereof. The method comprises the following steps: providing a substrate, and forming a grid stack on the substrate; forming a source / drain region and a source / drain epitaxial region on the substrate, wherein the source / drain epitaxial region is connected with the source / drain region, the length of the source / drain epitaxial region is larger than that of the source / drain region, and the length is the distance in the direction parallel with the channel length; forming a interlayer dielectric layer covering the grid stack, the source / drain region and the source / drain epitaxial region; and forming a contact plug on the source / drain epitaxial region. Correspondingly, the invention also provides a semiconductor structure. According to the invention, through adding the source / drain epitaxial region and arranging the contact plug on the source / drain epitaxial region, the area of the source / drain region is effectively reduced, and thus the area of the whole semiconductor device is reduced.

Description

technical field [0001] The invention relates to the field of manufacturing semiconductor devices, in particular to a semiconductor device and a manufacturing method thereof. Background technique [0002] With the development of semiconductor device manufacturing technology, integrated circuits with higher performance and stronger functions require greater component density, and the size, size and space of each component, between components or each component itself need to be further reduced. Therefore, semiconductor The requirements for process control in the device manufacturing process are relatively high. [0003] In the traditional semiconductor process, due to the limitation of the contact hole and the driving current, the length and width of the semiconductor device are limited, and it is not suitable to reduce it too much. The definition of length and width in the present invention is: the length is the distance in the direction parallel to the gate length, that is, ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L21/768H01L29/78H01L29/08
Inventor 朱慧珑尹海洲骆志炯
Owner BEIJING NAURA MICROELECTRONICS EQUIP CO LTD