Low-expenditure distributing structure and distributing method of network-on-chip router

Abstract

The invention discloses a low-expenditure distributing structure and distributing method of a network-on-chip router, which aim to solve the problems of high proportion of resources occupied by virtual channel distributing units, repeated work of the distribution of virtual channels and the distribution of switches, and long time delay in distribution in the distribution of virtual channels and the distribution of switches in the traditional virtual channel router. The low-expenditure distributing structure of a network-on-chip router comprises a first distributing structure and a second distributing structure, wherein the first distributing structure is distributed in output ports; each distributing unit of output ports comprises an invalid new request removing module, a PV: 1 arbitrator module and a simple virtual channel distributing module, and the first distributing structure completes the first step of arbitration and virtual channel distribution of the switch distribution. The second distributing structure is positioned in all input ports, each distributing unit of input ports is a V: 1 arbitrator module; the second distribution structure completes the second step of arbitration of the switch distribution; and the second distribution structure and the first distribution structure together complete the operation of virtual channel distribution and switch distribution of the virtual channel router. The low-expenditure distributing structure and the distributing method of a network-on-chip router have the advantages of short time delay and small size.

Description

technical field [0001] The invention belongs to the technical field of communication, and in particular relates to a low-overhead allocation structure and an allocation method of an on-chip network router used for virtual channel allocation and switch allocation in the router. Background technique [0002] As the CMOS process steps into the nanometer level, billions of transistors can be integrated on a single chip, the system-on-chip (SoC) design is becoming more and more complex, and more and more IP cores are integrated on the SoC chip. How to deal with the multi-core Communication issues are gaining increasing attention. The traditional bus structure seriously restricts performance improvement, because the bus structure has the following two bottlenecks: (1) Bandwidth limitation. Although the bus can effectively connect multiple IP cores, the bus address resources cannot be expanded infinitely with the increase of IP cores, and the bus cannot support simultaneous commun...

AI Technical Summary

Problems solved by technology

The traditional bus structure seriously restricts performance improvement, because the bus structure has the following two bottlenecks: (1) Bandwidth limitation

Although the bus can effectively connect multiple IP cores, the bus address resources cannot be expanded infinitely with the increase of IP cores, and the bus cannot support simultaneous communication of more than one pair of IP cores. When multiple IP cores compete for a bus, will cause severe blockage

(2) Clock problem

[0006] The virtual channel allocation of the traditional virtual channel router can simultaneously allocate multiple output virtual channels of the same output port to different input virtual channel requests, while the switch allocation follows the two-step arbitration principle, and its second stage allocation is from the same output port Arbitrating one of multiple successfully assigned output virtual channels, which leads to duplication of virtual channel assignment compared to switch assignment

[0007] There are a total of P*V P*V:1 arbitrators in the second stage of virtual channel allocation of traditional virtual channel routers. The size and number of arbitrators will increase sharply with the number of ports or virtual channels. Therefore, virtual channels Allocation occupies a large proportion of router resources

Images