A method of manufacturing an interconnect structure containing an air gap

A technology of interconnection structure and manufacturing method, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of small process window and poor sealing integrity, and achieve simplified process, ensure integrity, and large process window. Effect
CN102881643BActive Publication Date: 2017-04-19SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
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Patent Information

Authority / Receiving Office
CN Β· China
Patent Type
Patents(China)
Current Assignee / Owner
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
Publication Date
2017-04-19

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Abstract

The invention discloses a method for manufacturing an interconnection structure containing air gaps. The method includes: forming a first sacrificial layer on a substrate; forming a metal interconnection line in the first sacrificial layer; depositing and etching a second sacrificial layer to form a narrow-end-up peak structure which is connected with a sacrificial medium of the first sacrificial layer; depositing a first medium layer and removing the first medium layer of the upper surface of the second sacrificial layer so as to form a releasing opening at the top of the peak structure; removing sacrificial media of the first sacrificial layer and the second sacrifical layer; and depositing a second medium layer to form the air gaps. By the method, sealing integrity of the air gaps can be guaranteed and the interconnection structure has a larger process window.
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Description

technical field

[0001] The invention relates to the field of semiconductor integrated circuits, in particular to a method for manufacturing an interconnection structure with an air gap. Background technique

[0002] As integrated circuits (Integrated Circuit, IC) continue to shrink according to Moore's Law, the integration level is getting higher and higher, and the various performances of the devices are also demanding higher and higher requirements, among which the back-end process (BEOL, Back End of Line) The introduced resistance-capacitance delay (RC Delay) becomes an important factor that cannot be ignored more and more. The resistance-capacitance time delay is proportional to the resistance of the metal connection and the parasitic capacitance between the fill medium and the metal:

[0003] Ο„βˆRC inttot =R(C IMD +C ILD ) Formula 1)

[0004] Where R is the resistance of the metal connection, C IMD and C ILD They are the capacitance between metal wirings and the c...

Claims

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