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Reconfigurable delta-sigma modulator adc using noise coupling

An analog-to-digital converter and modulator technology, applied in the field of reconfigurable analog-to-digital converter modulator structure

Inactive Publication Date: 2013-01-23
MEDIATEK SINGAPORE PTE LTD SINGAPORE
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

A method based on a phase-locked loop (Phase Loop Lock, hereinafter referred to as PLL) bias generator is proposed, but this requires additional circuitry

Method used

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  • Reconfigurable delta-sigma modulator adc using noise coupling
  • Reconfigurable delta-sigma modulator adc using noise coupling
  • Reconfigurable delta-sigma modulator adc using noise coupling

Examples

Experimental program
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Embodiment Construction

[0017] The present invention proposes a novel arrangement in which a reconfigurable analog-to-digital converter modulator is provided which allows power consumption to be proportional to the input signal bandwidth.

[0018] figure 1 It is an overview schematic diagram according to the present invention. The modulator structure 2 includes a first ADC unit (cell) 4 and a second ADC unit 6 , wherein the first ADC unit 4 and the second ADC unit 6 receive an analog signal U. The first analog-to-digital converter unit 4 and the second analog-to-digital converter unit 6 mutually provide noise quantization. The output signals V1 and V2 of the first analog-to-digital converter unit 4 and the second analog-to-digital converter unit 6 are provided to an adder module 8 . Adder module 8 provides its output to divider module 10 . The divider module 10 performs a division on the output of the adder module 8 , by 2 in this embodiment. The first ADC unit 4 and the second ADC unit 6 act as ...

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PUM

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Abstract

A reconfigurable analog-to-digital (ADC) modulator structure that includes a plurality of ADC structures being coupled to each other through their respective noise quantization transfer functions. Each ADC structure receives as input an analog signal and each ADC structure outputting a plurality of first output signals. An adder module receives the first output signals and performs addition on the first output signals and generates a second output signal. A division module receives the second output signal and performs division on the second output signal by a predetermined factor.

Description

technical field [0001] The present invention relates to the field of Analog-to-Digital Converters (Analog-to-Digital Converters, ADCs), in particular to reconfigurable ADC modulator structures using noise coupling. Background technique [0002] Today, wireless communication receivers must support many different communication standards, such as Global System for Mobile Communications (GSM), Enhanced Data rate for GSM Evolution (hereinafter referred to as EDGE), time division synchronous code division multiple access (Time Division-Synchronous Code Division Multiple Access, hereinafter referred to as TD-SCDMA), wideband code division multiple access (Wide band Code Division Multiple Access, hereinafter referred to as WCDMA), high-speed downlink Packet access (High Speed ​​Downlink Packet Access+, hereinafter referred to as HSPA+), and long term evolution technology (Long Term Evolution, hereinafter referred to as LTE). This enables the wireless device to adapt to the availabl...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/12
CPCH03M3/326H03M1/12H03M3/396H03M3/39
Inventor 艾曼·夏柏哈利尔·基珀
Owner MEDIATEK SINGAPORE PTE LTD SINGAPORE