Level shifter for differential signals with balanced transition times

Abstract

A level shifter (400) and method are provided for balancing rise and fall times of a signal. An input circuit (420, 413) receives a differential logic signal (Inp, Inn) with two complimentary logic levels. A level transition balancing circuit (420) balances the rise and fall times of a level shifted version of each complimentary logic level during a transition from a first to a second of the logic levels and a level shift. A logic element (430) stores and provides outputs (outp, ounn) of the level shifted versions of the logic levels. The level transition balancing circuit (420) includes a capacitor (421) in parallel with a field-effect transistor (422) for each input. The capacitor destabilizes inputs to the logic element and balances the transition using the capacitance and a level (435, 436) previously stored in the logic element.

Description

technical field [0001] The present invention relates to high speed receivers and related circuits, and more particularly, to latch-based level shifters with balanced rise and fall times. Background technique [0002] Digital circuits typically use consistent logic levels for internal signals. However, the logic levels may vary from system to system, and even within various subsystem circuits within the same system. Level shifters can be used to interface digital circuits that use one logic level to digital circuits that use another logic level. Multiple level shifters may be used, such as one in each system where bi-directional shifting is required. For example, the driver can transition from internal logic levels to levels compatible with standard interface line levels. For example, line receivers can translate from interface levels to internal voltage levels. Examples of standard interface levels include Transistor-to-Transistor Logic (TTL) or Complementary Metal Oxide...

AI Technical Summary

Problems solved by technology

[0004] While simple level shifters are available in the prior art that accurately and adequately translate the levels associated with an input logic signal, a disadvantage of such circuits is that they can make time-domain characteristics of the signal such as duty cycle ) distortion due to mismatched rise / fall transitions that do not correspond precisely enough to the timing characteristics of the original signal for high-speed digital communication applications

This matching, or corresponding lack thereof, can adversely cause jitter, data errors, etc.

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