Array substrate, manufacture method thereof and display device including array substrate

Abstract

The invention discloses an array substrate manufacturing method and relates to the technical field of displaying. The array substrate manufacturing method comprises the following steps of S1 forming a graph including a grid electrode, a grid line and a grid insulating layer on a substrate; S2 forming a graph including an active layer and a channel region; S3 forming a graph including a source drain electrode and a data line; and S4 forming a graph including a pixel electrode and a passivation layer. The invention further discloses an array substrate manufactured by means of the method and a display device including the array substrate. The active layer and a channel are first manufactured, all of dry etching processes are finished before the source drain electrode is manufactured, electrostatic discharge of a data metal layer caused by the fact that the array substrate with the data metal layer is placed into a dry etching device reaction cavity is avoided, accordingly the problem that the electrostatic discharge causes circuit breakdown and damages a circuit structure, and further the product yield is improved.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display device. Background technique [0002] In the manufacturing process of thin film transistor liquid crystal display (TFT LCD), preventing or mitigating the occurrence of electrostatic discharge (ESD) is an important issue. During the manufacturing process of the array substrate, electrostatic discharge will cause circuit breakdown, damage the circuit structure, cause problems such as short circuit or open circuit, and seriously affect the product yield. [0003] The existing etching process for forming the source and drain electrodes is very prone to electrostatic discharge, which destroys the pattern of the data metal layer, or causes it to be short-circuited with the gate metal layer. The main reason is that after the array substrate with the data metal layer enters the reaction chamber of the dry etching...

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Problems solved by technology

[0007] It can be seen from the above two process flows that after the source and drain electrodes are finally etched, there will be a dry etching of the N+ active layer, which will cause electrostatic discharge on the data metal layer

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